199773 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details; Address generation devices; Devices for accessing memories, e.g. details of addressing circuits; Accessing single arrays Scan chain
Scannable SRAM
#2SCAN REGISTER CIRCUIT GENERATING POSITION INDEX SIGNAL THROUGH FAIL-BIT SCAN OPERATION AND MEMORY DEVICE INCLUDING THE SAME
#3Scannable Memory Subsystem
#4Memory apparatus having a memory output masking mechanism
#5MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE
#6TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE
#7DISTRIBUTED MRAM CONFIGURATION BIT AND METHOD OF REPAIR
#8Method for Scanning a Memory Array
#9Fully Scannable Memory Arrays
#10AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN
#11Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset
#12INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND COMPUTER-PROGRAM PRODUCT
#13SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
#14Register Bank Architecture with Latches
#15Programmable logic device with design for test functionality
#16Integrated circuit having test circuitry for memory sub-systems
#17Memory device with serial and parallel testing structure for sensing amplifiers
#18Programmable logic device with design for test functionality
#19Memory device, memory test circuit and memory test method thereof having repair information maintaining mechanism
#20Scan chain compression for testing memory of a system on a chip
#21Memory device architecture coupled to a system-on-chip
#22Single “A” latch with an array of “B” latches
#23JTAG registers with concurrent inputs
#24Memory device with analog measurement mode features
#25Method and circuit for scan dump of latch array
#26Method and circuit for row scannable latch array
#27Test access port architecture to facilitate multiple testing modes
#28Circuit and associated chip
#29Delay fault testing of pseudo static controls
#30Memory device architecture coupled to a System-on-Chip
#31Direct memory access using JTAG cell addressing
#32JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION
#33JTAG registers with concurrent inputs
#34Memory device with analog measurement mode features
#35Digital circuit testing and analysis module, system and method thereof
#36Memory device with improved sensing structure
#37Test access port architecture to facilitate multiple testing modes
#38Non-volatile computer data storage production-level programming
#39System including hierarchical memory modules having different types of integrated circuit memory devices
#40Test access port architecture to facilitate multiple testing modes
#41Delay fault testing of pseudo static controls
#42Scan chain techniques and method of using scan chain structure
#43Scannable-latch random access memory
#44Simultaneous scan chain initialization with disparate latches
#45Memory circuit and testing method thereof
#46Simultaneous scan chain initialization with disparate latches
#47Multi-port register file device and method of operation in normal mode and test mode
#48Integrated circuit fault detection
#49Register array having groups of latches with single test latch testable in single pass
#50Delay fault testing of pseudo static controls
#51Semiconductor device and diagnostic method therefor
#52Semiconductor integrated circuit
#53Embedded memory testing with storage borrowing
#54Sense amplifier flip-flop with embedded scan logic and level shifting functionality
#55Scan cell for dual port memory applications
#56Gate driving circuit and method for detecting same, array substrate and display apparatus
#57Implementing register array (RA) repair using LBIST
#58System including hierarchical memory modules having different types of integrated circuit memory devices
#59High accuracy leakage detection through low voltage biasing
#60Scan compression architecture for highly compressed designs and associated methods
#61System including hierarchical memory modules having different types of integrated circuit memory devices
#62Circuit for testing integrated circuits
#63Scan chain for memory sequential test
#64Circuit techniques for efficient scan hold path design
#65Scannable memories with robust clocking methodology to prevent inadvertent reads or writes
#66Scan compression architecture for highly compressed designs and associated methods
#67Method for performing built-in self-tests
#68Circuit for testing integrated circuits
#69Reconfigurable memory interface circuit to support a built-in memory scan chain
#70Integrated clock architecture for improved testing
#71Probeless testing of pad buffers on wafer
#72Input circuit
#73Pad switch cells selectively coupling test leads to test pads
#74Non-volatile semiconductor memory device
#75Semiconductor apparatus and semiconductor system for outputting internal information according to various mode and method for outputting internal information thereof
#76Reconfigurable connections for stacked semiconductor devices
#77Scan path switch testing of output buffer with ESD
#78Circuit for testing integrated circuits
#79METHOD AND DEVICE FOR PROTECTING INFORMATION CONTAINED IN AN INTEGRATED CIRCUIT
#80Input buffer, test switches and switch control with serial I/O
#81Testing embedded memories in an integrated circuit
#82Low power design using a scan bypass multiplexer as an isolation cell
#83Data transfer circuit
#84Supporting scan functions within memories
#85Semiconductor integrated circuit
#86Reconfigurable connections for stacked semiconductor devices
#87Scalable scan system for system-on-chip design
#88At-speed scan testing of memory arrays
#89TEST ACCESS CONTROL APPARATUS AND METHOD THEREOF
#90On-chip logic to support compressed X-masking for BIST
#91SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS, OUTPUT DATA DIFFUSION METHOD, AND PROGRAM
#92Compressing test responses using a compactor
#93System, apparatus, and method for memory built-in self testing using microcode sequencers
#94Secure scan design
#95Input/output compression and pin reduction in an integrated circuit
#96SEMICONDUCTOR MEMORY DEVICE AND SELF-TEST METHOD OF THE SAME
#97Transparent test method and scan flip-flop
#98Method and apparatus for testing the connectivity of a flash memory chip
#99Test interface for memory elements
#100Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)
#101System including hierarchical memory modules having different types of integrated circuit memory devices
#102High performance pulsed storage circuit
#103System in package with built-in test-facilitating circuit
#104METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN
#105Method and circuit for protection of sensitive data in scan mode
#106Semiconductor device testing
#107Method and apparatus for securing digital information on an integrated circuit during test operating modes
#108Address controlling in the MBIST chain architecture
#109Data controlling in the MBIST chain architecture
#110Scan circuitry controlled switch connecting buffer output to test lead
#111Techniques for logic built-in self-test diagnostics of integrated circuit devices
#112Fault diagnosis of compressed test responses
#113Scalable scan-based test architecture with reduced test time and test power
#114Apparatus for testing embedded memory read paths
#115Testing embedded memories in an integrated circuit
#116Digital circuits and methods for testing a digital circuit
#117Test circuit capable of sequentially performing boundary scan test and test method thereof
#118Scanned memory testing of multi-port memory arrays
#119Reconfigurable connections for stacked semiconductor devices
#120Memory sense scan circuit and test interface
#121System, apparatus, and method for memory built-in self testing using microcode sequencers
#122Semiconductor storage device and test method therefor
#123Shift register latch with embedded dynamic random access memory scan only cell
#124Apparatus for efficiently loading scan and non-scan memory elements
#125Probeless testing of pad buffers on wafer
#126Nonvolatile semiconductor memory system
#127COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS
#128Circuit arrangement, electronic mechanism, electrical turn out and procedures for the operation of one circuit arrangement
#129Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design
#130Method and dual interlocked storage cell latch for implementing enhanced testability
#131Structure for system for and method of performing high speed memory diagnostics via built-in-self-test
#132Partial good integrated circuit and method of testing same
#133Input/output compression and pin reduction in an integrated circuit
#134Scanning Latches Using Selecting Array
#135MEMORY READ CIRCUIT AND MEMORY APPARATUS USING THE SAME
#136Scanning Latches Using Selecting Array
#137Compressing test responses using a compactor
#138Method and apparatus for testing embedded cores
#139Progressive random access scan circuitry
#140Test circuit for testing command signal at package level in semiconductor device
#141System and method for performing high speed memory diagnostics via built-in-self-test
#142FBM generation device and FBM generation method
#143Merged MISR and output register without performance impact for circuits under test
#144SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
#145Daisy chainable memory chip
#146Daisy chainable memory chip
#147Cell supporting scan-based tests and with reduced time delay in functional mode
#148Partial good integrated circuit and method of testing same
#149Register file cell with soft error detection and circuits and methods using the cell
#150Method for at-speed testing of memory interface using scan
#151Method and apparatus for testing the connectivity of a flash memory chip
#152Methods and apparatus for improved memory access
#153Input/output buffer test circuitry and leads additional to boundary scan
#154Semiconductor integrated circuit apparatus and control method thereof
#155Semiconductor memory device operating using read only memory data
#156Test circuit for semiconductor device
#157Scan Read Block Wherein a Scan Latch Circuit and a Bit Cell Have Substantially Identical Circuit Structures
#158Semiconductor integrated circuit and testing method thereof
#159Semiconductor integrated circuit
#160Scan path circuit and semiconductor integrated circuit comprising the scan path circuit
#161Systems and methods for improved memory scan testability
#162Pulsed flop with scan circuitry
#163Method and apparatus to save and restore context using scan cells
#164Serial data input/output method and apparatus
#165Scanned memory testing of multi-port memory arrays
#166Signal integrity self-test architecture
#167Test circuit and test method
#168Method for enabling scan of defective ram prior to repair
#169Integrated scannable interface for testing memory
#170Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality
#171Digital storage element with dual behavior
#172Digital storage element architecture comprising integrated multiplexer and reset functionality
#173Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality
#174Non-volatile memory cell integrated with a latch
#175RAM testing apparatus and method
#176Semiconductor memory device and testing method thereof
#177Merged MISR and output register without performance impact for circuits under test
#178Semiconductor integrated circuit having test function and manufacturing method
#179Content addressable memory including a dual mode cycle boundary latch
#180Compilable memory structure and test methodology for both ASIC and foundry test environments
#181System and method of testing a plurality of memory blocks of an integrated circuit in parallel
#182Methods and apparatus for testing a memory
#183Register file and its storage device
#184Semiconductor integrated circuit
#185Semiconductor integrated circuit having bonding optional function
#186Fault diagnosis of compressed test responses having one or more unknown states
#187Adaptive fault diagnosis of compressed test responses
#188Fault diagnosis of compressed test responses
#189Acceleration of the programming of a memory module with the aid of a boundary scan (BSCAN) register
#190Semiconductor device
#191Scanning latches using selecting array
#192System and method for write-enable bypass testing in an electronic circuit
#193System and method for front-end bypass testing in an electronic circuit
#194System and scanout circuits with error resilience circuit
#195Error detecting circuit
#196Scan enabled storage device
#197Method and/or apparatus for generating a write gated clock signal
#198Circuit and method for storing a signal using a latch shared between operational and diagnostic paths
#199Method and apparatus for high speed testing of latch based random access memory
#200Cache late select circuit
#201Output driver with pulse to static converter
#202Testing memory access signal connections
#203Testing memories using algorithm selection
#204Method and device for saving and setting a circuit state of a microelectronic circuit
#205Microcomputer, a method for protecting memory and a method for performing debugging
#206Methods and apparatus for improved memory access
#207Memory testing
#208Semiconductor test apparatus and method thereof and multiplexer and method thereof
#209Scan test method, device, and system
#210Mechanism to enhance observability of integrated circuit failures during burn-in tests
#211Partial good integrated circuit and method of testing same
#212Method and circuit for scan testing latch based random access memory
#213Method of efficiently loading scan and non-scan memory elements
#214Method and arrangement for testing output circuits of high speed semiconductor memory devices
#215Fault tolerant semiconductor system
#216Systems and methods for scan chain stitching
#217Securing access to integrated circuit scan mode and data