199771 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details; Address generation devices; Devices for accessing memories, e.g. details of addressing circuits Accessing single arrays
Sub-classes:APPARATUSES, SYSTEMS AND METHODS FOR BANK OPTION BROADCASTS
#2APPARATUS INCLUDING INTERNAL CAPACITY MEASUREMENT AND ASSOCIATED METHODS
#3PHYSICAL REDUNDANCY AND MAPPING OF ADDRESSES FOR ACCESS LINES IN A MEMORY DEVICE
#4METHOD OF PROCESSING METADATA AND MEMORY DEVICE PERFORMING THE METHOD
#5VARIABLE RESISTANCE FOR CURRENT CONTROL IN NONVOLATILE MEMORY ARRAYS
#6NON-DESTRUCTIVE MEMORY SELF-TEST
#7Logging a Memory Address Associated with Faulty Usage-Based Disturbance Data
#8DISTRIBUTED MRAM CONFIGURATION BIT AND METHOD OF REPAIR
#9MEMORY, MEMORY SYSTEM, OPERATION METHOD OF THE MEMORY, AND OPERATION OF THE MEMORY SYSTEM
#10Method for Scanning a Memory Array
#11Fully Scannable Memory Arrays
#12METHODS AND APPARATUS TO SELECT ADDRESSES FOR MEMORY TRAINING
#13Register Bank Architecture with Latches
#14METHOD AND APPARATUS OF INTEGRATING MEMORY STACKS
#15Memory, memory system, operation method of the memory, and operation of the memory system
#16Scan chain compression for testing memory of a system on a chip
#17Circuit and associated chip
#18Memory, memory system, operation method of the memory, and operation of the memory system
#19Apparatuses and methods for direct access hybrid testing
#20Cache array macro micro-masking
#21SEMICONDUCTOR DEVICE
#22Register array having groups of latches with single test latch testable in single pass
#23Monitoring a memory for retirement
#24Method and apparatus of integrating memory stacks
#25Memory device and test method thereof
#26Repairable semiconductor memory device and test methods for the same
#27Variable read delay system
#28Partial chip, and systems having the same
#29Methods for accessing a storage unit of a flash memory and apparatuses using the same
#30Address windowing for at-speed bitmapping with memory built-in self-test
#31Performing stuck-at testing using multiple isolation circuits
#32Non-volatile memory array configurable for high performance and high density
#33Method and apparatus pertaining to a ferroelectric random access memory
#34Automatic scrambling of input/output data according to row addresses in a semiconductor memory device
#35Semiconductor device
#36Semiconductor memory device, memory module having the same, the test method of memory module
#37Test circuit for semiconductor device
#38Acceleration of the programming of a memory module with the aid of a boundary scan (BSCAN) register
#39Apparatuses and methods for direct access hybrid testing
#40Memory device providing bad column repair and method of operating same
#41Semiconductor device having a test circuit