199791 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Marginal testing, e.g. race, voltage or current testing Characteristic
MEMORY TEST CIRCUIT, MEMORY ARRAY, AND TESTING METHOD OF MEMORY ARRAY
#2SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
#3Memory device including sense amplifying circuit
#4METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRATE FOR IMPROVED PERFORMANCE, AND ASSOCIATED SYSTEMS AND METHODS
#5Memory test circuit, memory array, and testing method of memory array
#6Control method, semiconductor memory, and electronic device
#7Mediating directed refresh management induced row hammer and row access strobe (RAS) clobber failures
#8ROW ACCESS STROBE (RAS) CLOBBER AND ROW HAMMER FAILURE MITIGATION
#9Row access strobe (RAS) clobber and row hammer failures using a deterministic protocol
#10Methods for optimizing semiconductor device placement on a substrate for improved performance, and associated systems and methods
#11Systems and methods for correcting data errors in memory
#12Apparatus, system, and method for trimming analog temperature sensors
#13Memory device
#14Sensor for performance variation of memory read and write characteristics
#15Device and method for data-writing
#16Systems and methods for correcting data errors in memory
#17Method of improving read current stability in analog non-volatile memory cells by screening memory cells
#18Inter-hamming difference analyzer for memory array and measuring and testing methods for inter-hamming differences of memory array
#19Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device
#20Structure and method for testing three-dimensional memory device
#21Memory device for changing pass voltage
#22Sensor for performance variation of memory read and write characteristics
#23Device and method for data-writing
#24Erase page check
#25Memory array and measuring and testing methods for inter-hamming differences of memory array
#26Tamper-proof storage using signatures based on threshold voltage distributions
#27Memory device including a deterioration level detection circuit
#28Systems and methods for correcting data errors in memory
#29Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
#30Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure
#31Method, system and device for testing correlated electron switch (CES) devices
#32Detecting random telegraph noise defects in memory
#33Method for testing MRAM device and test apparatus thereof
#34Structure and method for testing three-dimensional memory device
#35Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature
#36Magnetic field generator
#37Device and method for data-writing
#38Method for continuous tester operation during multiple stage temperature testing
#39Testing and setting performance parameters in a semiconductor device and method therefor
#40Method and system for determining temperature using a magnetic junction
#41Semiconductor device
#42Method for SRAM yield estimation
#43Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing
#44Computing device executing program performing method of analyzing power noise in semiconductor device, semiconductor device design method, and program storage medium storing program
#45Method for low power operation and test using DRAM device
#46Memory device and memory system performing request-based refresh, and operating method of the memory device
#47Tamper-proof storage using signatures based on threshold voltage distributions
#48Virtual timer for data retention
#49Apparatus and method for physically unclonable function (PUF) for a memory array
#50Memory array and measuring and testing methods for inter-hamming differences of memory array
#51Apparatuses and methods for sensing a phase change test cell and determining changes to the test cell resistance due to thermal exposure
#52Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure
#53Read circuitry for electrostatic discharge switching memristive element
#54High speed and high precision characterization of VTsat and VTlin of FET arrays
#55Array power supply-based screening of static random access memory cells for bias temperature instability
#56Raid data loss prevention
#57Systems and methods for correcting data errors in memory susceptible to data loss when subjected to elevated temperatures
#58Background reference positioning and local reference positioning using threshold voltage shift read
#59Nonvolatile memory system with background reference positioning and local reference positioning
#60ESD detection apparatus and method applied to digital integrated circuit, and integrated circuit
#61Electrostatic discharge memristive element switching
#62Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
#63Device and method for data-writing
#64Memory and logic lifetime simulation systems and methods
#65Technologies for estimating remaining life of integrated circuits using on-chip memory
#66Semiconductor device and electronic device
#67Raid data loss prevention
#68Memory device and memory system performing request-based refresh, and operating method of the memory device
#69Memory module monitoring memory operation and power management method thereof
#70Addressable test circuit and test method for key parameters of transistors
#71Apparatus for physically unclonable function (PUF) for a memory array
#72On-chip test circuit for magnetic random access memory (MRAM)
#73Method and system for improving the radiation tolerance of floating gate memories
#74Digital test system
#75Static random-access memory (SRAM) sensor for bias temperature instability
#76Word line driver comprising NAND circuit
#77Computing device executing program performing method of analyzing power noise in semiconductor device, semiconductor device design method, and program storage medium storing program
#78Method and system for determining temperature using a magnetic junction
#79Method and system for improving the radiation tolerance of floating gate memories
#80Power loss test device and method for nonvolatile memory device
#81Methods, apparatus and system for TDDB testing
#82Electromagnet, tester and method of manufacturing magnetic memory
#83Testing and setting performance parameters in a semiconductor device and method therefor
#84Testing and setting performance parameters in a semiconductor device and method therefor
#85Testing and setting performance parameters in a semiconductor device and method therefor
#86NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations
#87Circuit and method for detection and compensation of transistor mismatch
#88Array power supply-based screening of static random access memory cells for bias temperature instability
#89Array power supply-based screening of static random access memory cells for bias temperature instability
#90Array power supply-based screening of static random access memory cells for bias temperature instability
#91Assist circuits for SRAM testing
#92Memory system, method of programming the memory system, and method of testing the memory system
#93Method of testing semiconductor memory device, test device, and computer readable recording medium for recording test program for semiconductor memory device
#94Traffic and temperature based memory testing
#95Traffic and temperature based memory testing
#96Tester for testing magnetic memory
#97Shaping codes for memory
#98Method and system for improving the radiation tolerance of floating gate memories
#99Dynamic static random access memory (SRAM) array characterization using an isolated bit-line
#100Data recovery from blocks with gate shorts
#101Memory, memory system including the same and method for operating memory
#102Method of detecting transistors mismatch in a SRAM cell
#103Recovery of interfacial defects in memory cells
#104Digital test system
#105System and method for writing pilot data interspersed with user data for estimating disturbance experienced by user data
#106Self-diagnosing method of a volatile memory device and an electronic device performing the same
#107Estimation method, estimation device, and inspection device for variable resistance element, and nonvolatile memory device
#108Memory with bit line current injection
#109Memory with redundant sense amplifier
#110Devices and methods for measurement of magnetic characteristics of MRAM wafers using magnetoresistive test strips
#111Electronic device
#112Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor
#113Method and apparatus for measuring alpha particle induced soft errors in semiconductor devices
#114Memory subsystem performance based on in-system weak bit detection
#115Flash interface error injector
#116Flash interface error injector
#117Read margin measurement in a read-only memory
#118SERIAL ADVANCED TECHNOLOGY ATTACHMENT DUAL IN-LINE MEMORY MODULE DEVICE HAVING TESTING CIRCUIT FOR CAPACITOR
#119Semiconductor memory device having programmable select transistors within memory units
#120Method of executing wear leveling in a flash memory device according to ambient temperature information and related flash memory device
#121Memory device having collaborative filtering to reduce noise
#122Fault-aware mapping for shared last level cache (LLC)
#123Test circuit for testing refresh circuitry of a semiconductor memory device
#124Resistance memory cell and operation method thereof
#125Memory cell having flexible read/write assist and method of using
#126Method and system for controlling loss of reliability of non-volatile memory
#127Memory with redundant sense amplifier
#128Temperature-profiled device fingerprint generation and authentication from power-up states of static cells
#129Direct relative measurement of memory durability
#130Memory with bit line current injection
#131Memory with variable strength sense amplifier
#132Memory with bit line capacitive loading
#133SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor
#134Oscillato based on a 6T SRAM for measuring the bias temperature instability
#135Static noise margin monitoring circuit and method
#136Semiconductor memory device changing refresh interval depending on temperature
#137Tracking capacitive loads
#138METHOD AND DEVICE FOR ESTIMATING DAMAGE TO A MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT
#139ELECTRONIC DEVICE AND METHOD FOR TESTING ENDURANCE OF MEMORY
#140Quantifying the read and write margins of memory bit cells
#141Sensing phase-change memory/test cells for determining whether a cell resistance has changed due to thermal exposure
#142Test structures, methods of manufacturing thereof, test methods, and MRAM arrays
#143SEMICONDUCTOR MEMORY DEVICE
#144Semiconductor memory device and method of testing the same
#145Static random access memory test structure
#146VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY
#147Integrated circuit chip and semiconductor memory device
#148Determination of series resistance of an array of capacitive elements
#149Pilot placement for non-volatile memory
#150Memory and Method of Adjusting Operating Voltage thereof
#151Non-volatile memory management system with load leveling and method of operation thereof
#152Method of screening static random access memory cells for positive bias temperature instability
#153On-Chip Delay Measurement Through a Transistor Array
#154Low temperature BEOL compatible diode having high voltage margins for use in large arrays of electronic components
#155Array power supply-based screening of static random access memory cells for bias temperature instability
#156SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF
#157Semiconductor memory device and test method therefor
#158Semiconductor apparatus and testing method thereof
#159Input power measuring device
#160Read threshold setting based on temperature integral
#161Apparatus and method for computing coupling noise voltage occurring in flash memory device
#162Method of detecting defects in a semiconductor device and semiconductor device using the same
#163Temperature-profiled device fingerprint generation and authentication from power-up states of static cells
#164Bypass capacitor circuit and method of providing a bypass capacitance for an integrated circuit die
#165Devices and method for wear estimation based memory management
#166Identifying and correcting a bit error in a FRAM storage unit of a semiconductor device
#167Phase change random access memory apparatus performing a firing operation
#168Control circuit and data hold device using the control circuit
#169Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits
#170Threshold voltage digitizer for array of programmable threshold transistors
#171Method and apparatus pertaining to a ferroelectric random access memory
#172Data management in flash memory using probability of charge disturbances
#173Data management in flash memory using probability of charge disturbances
#174Single event-upset controller wrapper that facilitates fault injection
#175Circuit and method for RAS-enabled and self-regulated frequency and delay sensor
#176On-Chip Delay Measurement Through a Transistor Array
#177System For Signal Detection of Specimen Using Magnetic Resistance Sensor and Detecting Method of The Same
#178Rejuvenation of analog memory cells
#179Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh
#180Threshold voltage digitizer for array of programmable threshold transistors
#181Methods, apparatus and articles of manufacture to diagnose temperature-induced memory errors
#182Universal test structures based SRAM on-chip parametric test module and methods of operating and testing
#183Semiconductor integrated circuit
#184Indicator-based product design optimization to find defective and non-defective status
#185Structure and methods for measuring margins in an SRAM bit
#186Semiconductor memory device changing refresh interval depending on temperature
#187Closed-loop soft error rate sensitivity control
#188Test method and device for memory device
#189Electronic equipment system and semiconductor integrated circuit controller
#190Threshold voltage digitizer for array of programmable threshold transistors
#191Static noise margin estimation
#192Test apparatus and test method for testing a memory device
#193Securely field configurable device
#194Accessing memory cells in a memory circuit
#195DISPLAY CONFIGURED TO DISPLAY HEALTH STATUS OF A MEMORY DEVICE
#196Semiconductor memory device and test method therefor
#197Structure and methods for measuring margins in an SRAM bit
#198HIGH-SPEED CAPACITOR LEAKAGE MEASUREMENT SYSTEMS AND METHODS
#199Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels
#200ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH DEFECTIVE MEMORY DEVICES
#201Rejuvenation of analog memory cells
#202Semiconductor memory device having shared temperature control circuit
#203Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith
#204Method for evaluating SRAM memory cell and computer readable recording medium which records evaluation program of SRAM memory cell
#205Memory module including environmental optimization
#206Apparatus for the dynamic detection, selection and deselection of leaking decoupling capacitors
#207Method and apparatus for measuring statistics of dram parameters with minimum perturbation to cell layout and environment
#208Semiconductor device identifier generation method and semiconductor device
#209Semiconductor memory device
#210Temperature sensor capable of reducing test mode time
#211Temperature-profiled device fingerprint generation and authentication from power-up states of static cells
#212Identification circuit with repeatable output code
#213Methods for characterizing device variation in electronic memory circuits
#214Semiconductor memory device and thermal code output circuit capable of correctly measuring thermal codes
#215Volatile device keys and applications thereof
#216Semiconductor memory device with temperature sensing device and operation thereof
#217Electrical erasable programmable memory transconductance testing
#218Automatic shutdown or throttling of a BIST state machine using thermal feedback
#219Efficient interference cancellation in analog memory cell arrays
#220Method for Operating a Non-Volatile Charge-Trapping Memory Device and Method for Determining Programming/Erase Conditions
#221METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE
#222Semiconductor memory device
#223On-chip characterization of noise-margins for memory arrays
#224Circuits and methods for characterizing device variation in electronic memory circuits
#225Status of overall health of nonvolatile memory
#226On die thermal sensor of semiconductor memory device and method thereof
#227Semiconductor memory device changing refresh interval depending on temperature
#228Threshold voltage digitizer for array of programmable threshold transistors
#229Efficient and systematic measurement flow on drain voltage for different trimming in flash silicon characterization
#230INTEGRATED CIRCUIT INCLUDING DECOUPLING CAPACITORS THAT CAN BE DISABLED
#231Semiconductor memory device changing refresh interval depending on temperature
#232Memory system and semiconductor integrated circuit
#233ACTIVE CANCELLATION MATRIX FOR PROCESS PARAMETER MEASUREMENTS
#234Semiconductor device with self refresh test mode
#235Programmable heavy-ion sensing device for accelerated DRAM soft error detection
#236Programmable heavy-ion sensing device for accelerated DRAM soft error detection
#237Method and apparatus to adjust voltage for storage location reliability
#238Semiconductor integrated circuit
#239Pulsed ring oscillator circuit for storage cell read timing evaluation
#240Memory device with reduced standby power consumption and method for operating same
#241Semiconductor memory device with a reference or dummy cell for testing
#242Pilot placement for non-volatile memory
#243Method of testing semiconductor apparatus
#244Circuit and method for detecting skew of transistors in a semiconductor device
#245SEMICONDUCTOR DEVICE AND TRIMMING METHOD
#246Systems and methods for maintaining performance at a reduced power
#247METHOD FOR TESTING FLASH MEMORY POWER LOSS RECOVERY
#248Method for validation of thermal solution for an electronic component
#249Memories, method of storing data in memory and method of determining memory cell sector quality
#250Method and system of analyzing failure in semiconductor integrated circuit device
#251Test method for semiconductor device
#252SRAM static noise margin test structure suitable for on chip parametric measurements
#253Method and device for verifying output signals of an integrated circuit
#254ID installable LSI, secret key installation method, LSI test method, and LSI development method
#255Crystal oscillator emulator
#256Method and system for independent control of voltage and its temperature co-efficient in non-volatile memory devices
#257Real-time optimized testing of semiconductor device
#258High bandwidth datapath load and test of multi-level memory cells
#259Method and circuit arrangement for operating a volatile random access memory as a detector
#260Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
#261Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh
#262Memory system and semiconductor integrated circuit
#263Integrated semiconductor memory and method for operating an integrated semiconductor memory
#264REFERENCE VOLTAGE GENERATING CIRCUIT
#265Memory test engine
#266Semiconductor memory and refresh cycle control method
#267Measuring apparatus, measuring method, testing apparatus, testing method, and electronic device
#268Semiconductor memory apparatus having noise generating block and method of testing the same
#269Magnetic random access memory
#270Memory array with readout isolation
#271Integrated Semiconductor Memory with Refreshing of Memory Cells
#272Semiconductor memory device with temperature sensing device and operation thereof
#273Memory array with readout isolation
#274Nonvolatile semiconductor memory device and method for testing the same
#275Automatic shutdown or throttling of a bist state machine using thermal feedback
#276Memory array with readout isolation
#277Circuit and method for adjusting threshold drift over temperature in a CMOS receiver
#278Method for estimating and reporting the life expectancy of flash-disk memory
#279Crystal oscillator emulator
#280Memory having count detection circuitry for detecting access frequency
#281Crystal oscillator emulator
#282Nonvolatile memory device and method thereof
#283High-speed capacitor leakage measurement systems and methods
#284Crystal oscillator emulator
#285Method and apparatus to adjust voltage for storage location reliability
#286Internally asymmetric method for evaluating static memory cell dynamic stability
#287Active cancellation matrix for process parameter measurements
#288Semiconductor memory device changing refresh interval depending on temperature
#289Method for evaluating leakage effects on static memory cell access time
#290Measuring method for a semiconductor memory, and semiconductor memory
#291Method and apparatus to detect electrical overstress of a device
#292Multi-chip package sharing temperature-compensated self-refresh signal and method thereof
#293On die thermal sensor of semiconductor memory device and method thereof
#294Temperature sensing circuit, voltage generation circuit, and semiconductor storage device
#295Semiconductor Integrated Circuit Device and Method of Testing the Same
#296Semiconductor integrated circuit device and method of testing the same
#297Signal integrity self-test architecture
#298Magnetic tunnel junction temperature sensors
#299Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
#300Bitline variable methods and circuits for evaluating static memory cell dynamic stability