ClassID:

199844

G11C2207/002 - page 2 - CPC Classification

Classification description:

Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Recent Application in this class:
#301
20070263466
2007-11-15

Semiconductor memory device

#302
20070258303
2007-11-08

Semiconductor memory device

#303
20070242539
2007-10-18

Semiconductor memory device

#304
20070242528
2007-10-18

Nonvolatile semiconductor memory device

#305
20070230262
2007-10-04

Semiconductor memory

#306
20070223272
2007-09-27

Semiconductor memory device

#307
20070217269
2007-09-20

Semiconductor memory device and driving method of semiconductor memory device

#308
20070217261
2007-09-20

Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis

#309
20070195631
2007-08-23

Control system for a dynamic random access memory and method of operation thereof

#310
20070195619
2007-08-23

Integrated circuit memory devices having multi-bit normal memory cells and single-bit redundant memory cells therein

#311
20070189079
2007-08-16

Memory devices with page buffer having dual registers and method of using the same

#312
20070147160
2007-06-28

Semiconductor memory device with sub-amplifiers having a variable current source

#313
20070147152
2007-06-28

Sense amplifier for semiconductor memory device

#314
20070140005
2007-06-21

Multi-level dynamic memory device

#315
20070139992
2007-06-21

Semiconductor memory device

#316
20070109904
2007-05-17

Memory core with single contacts and semiconductor memory device having the same

#317
20070109892
2007-05-17

Memory device and method of operating the same

#318
20070109891
2007-05-17

Semiconductor memory device and method for driving semiconductor memory device

#319
20070104003
2007-05-10

MEMORY DEVICE WITH AUXILIARY SENSING

#320
20070104002
2007-05-10

Semiconductor memory device with MOS transistors each having floating gate and control gate and method of controlling the same

#321
20070091715
2007-04-26

Semiconductor memory device

#322
20070076494
2007-04-05

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

#323
20070071130
2007-03-29

Signal transmission system using PRD method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied

#324
20070070758
2007-03-29

SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER AND SWITCH

#325
20070070755
2007-03-29

Semiconductor memory device having shared bit line sense amplifier scheme and driving method thereof

#326
20070070749
2007-03-29

Semiconductor memory device and data read and write method thereof

#327
20070070697
2007-03-29

Semiconductor memory device sharing a data line sense amplifier and a write driver in order to reduce a chip size

#328
20070047368
2007-03-01

Semiconductor memory device having layered bit line structure

#329
20070047356
2007-03-01

Wide databus architecture

#330
20070036008
2007-02-15

Semiconductor memory device

#331
20070019486
2007-01-25

High speed array pipeline architecture

#332
20070014181
2007-01-18

Semiconductor memory device having connected bit lines and data shift method thereof

#333
20070014180
2007-01-18

Device and method for selecting 1-row and 2-row activation

#334
20070014179
2007-01-18

Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations

#335
20070002674
2007-01-04

Semiconductor memory device having improved column selection lines and method of driving the same

#336
20060280020
2006-12-14

Memory data access scheme

#337
20060280001
2006-12-14

Semiconductor memory device provided with a write column selection switch and a read column selection switch separately

#338
20060256630
2006-11-16

Apparatus and method to reduce undesirable effects caused by a fault in a memory device

#339
20060256625
2006-11-16

Semiconductor memory device

#340
20060250869
2006-11-09

Semiconductor memory device having hierarchically structured data lines and precharging means

#341
20060239105
2006-10-26

Semiconductor memory device

#342
20060239059
2006-10-26

Memory array circuit with two-bit memory cells

#343
20060233038
2006-10-19

Semiconductor memory device

#344
20060221754
2006-10-05

Semiconductor memory device having a hierarchical bit line structure

#345
20060221665
2006-10-05

Semiconductor memory device for low voltage

#346
20060220680
2006-10-05

Hardware and software programmable fuses for memory repair

#347
20060209602
2006-09-21

Column selection signal generator of semiconductor memory device

#348
20060203587
2006-09-14

Partition of non-volatile memory array to reduce bit line capacitance

#349
20060198191
2006-09-07

Semiconductor integrated circuit device

#350
20060193190
2006-08-31

Multi-bank memory

#351
20060187702
2006-08-24

Memory integrated circuit, in particular an SRAM memory integrated circuit, and corresponding fabrication process

#352
20060176747
2006-08-10

Circuit for interfacing local bitlines with global bitline

#353
20060176729
2006-08-10

Local bit select with suppression of fast read before write

#354
20060171226
2006-08-03

Semiconductor memory device with column to be selected by bit line selection signal

#355
20060171215
2006-08-03

High density bitline selection apparatus for semiconductor memory devices

#356
20060171211
2006-08-03

Semiconductor memory device and method for multiplexing write data thereof

#357
20060158943
2006-07-20

Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor

#358
20060146623
2006-07-06

Semiconductor device

#359
20060146596
2006-07-06

Configurable storage device

#360
20060146593
2006-07-06

Method and circuit for reading a dynamic memory circuit

#361
20060139988
2006-06-29

Isolation device over field in a memory device

#362
20060126421
2006-06-15

Apparatus and methods for generating a column select line signal in semiconductor memory device

#363
20060126418
2006-06-15

Semiconductor memory device with hierarchical I/O line architecture

#364
20060109732
2006-05-25

Semiconductor memory device capable of operating at high speed

#365
20060098515
2006-05-11

Semiconductor memory device with column selecting switches in hierarchical structure

#366
20060092738
2006-05-04

Semiconductor memory device for low power system

#367
20060092735
2006-05-04

Method for measuring offset voltage of sense amplifier and semiconductor employing the method

#368
20060092732
2006-05-04

Semiconductor memory device for low power system comprising sense amplifier with operating voltages lower/higher than ground/voltage supply and auxiliary sense amplifier

#369
20060092731
2006-05-04

Semiconductor memory device for low power system

#370
20060092720
2006-05-04

Semiconductor memory

#371
20060087896
2006-04-27

Semiconductor memory having tri-state driver device

#372
20060083083
2006-04-20

Method and apparatus for synchronization of row and column access operations

#373
20060083078
2006-04-20

Memory device

#374
20060083063
2006-04-20

Memory devices with page buffer having dual registers and method of using the same

#375
20060062061
2006-03-23

Integrated circuit memory devices having hierarchical bit line selection circuits therein

#376
20060050574
2006-03-09

Memory device with column select being variably delayed

#377
20060034141
2006-02-16

Nonvolatile semiconductor memory with write global bit lines and read global bit lines

#378
20060034133
2006-02-16

Sense amplifier for semiconductor memory device

#379
20060028879
2006-02-09

Semiconductor device

#380
20060023493
2006-02-02

Apparatus and method to reduce undesirable effects caused by a fault in a memory device

#381
20060013041
2006-01-19

Nonvolatile memory structure with high speed high bandwidth and low voltage

#382
20050286291
2005-12-29

Dual access DRAM

#383
20050276091
2005-12-15

Semiconductor memory device

#384
20050265107
2005-12-01

Semiconductor memory device

#385
20050254332
2005-11-17

Method for bus capacitance reduction

#386
20050249019
2005-11-10

Bus connection circuit for read operation of multi-port memory device

#387
20050249018
2005-11-10

Multi-port memory device

#388
20050249015
2005-11-10

Multi-port memory device with global data bus connection circuit

#389
20050243621
2005-11-03

Semiconductor memory device having hierarchically structured data lines and precharging means

#390
20050242864
2005-11-03

Semiconductor device, semiconductor system, and digital delay circuit

#391
20050237805
2005-10-27

Semiconductor non-volatile storage device

#392
20050232011
2005-10-20

Memory devices with page buffer having dual registers and method of using the same

#393
20050231995
2005-10-20

Nonvolatile ferroelectric memory device

#394
20050226081
2005-10-13

Semiconductor memory device

#395
20050226025
2005-10-13

Semiconductor memory device for sensing voltages of bit lines in high speed

#396
20050207242
2005-09-22

Semiconductor memory device with a hierarchical bit lines, having row redundancy means

#397
20050206411
2005-09-22

Device for generating a bit line selection signal of a memory device

#398
20050190631
2005-09-01

Method for bus capacitance reduction

#399
20050190588
2005-09-01

Semiconductor device

#400
20050180242
2005-08-18

Semiconductor storage device

#401
20050162955
2005-07-28

Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit

#402
20050146957
2005-07-07

Semiconductor memory device and data read and write method thereof

#403
20050141324
2005-06-30

Semiconductor memory device for high speed data access

#404
20050141323
2005-06-30

Semiconductor memory device for reducing lay-out area

#405
20050141307
2005-06-30

Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch

#406
20050128860
2005-06-16

Thin film magnetic memory device including memory cells having a magnetic tunnel junction

#407
20050127969
2005-06-16

Circuit for controlling a delay time of input pulse and method of controlling the same

#408
20050125591
2005-06-09

Semiconductor memory device having hierarchical bit line structure

#409
20050122813
2005-06-09

FeRAM and sense amplifier array having data bus pull-down sensing function and sensing method using the same

#410
20050122148
2005-06-09

Circuit for controlling pulse width

#411
20050117437
2005-06-02

Semiconductor memory device, write control circuit and write control method for the same

#412
20050117429
2005-06-02

Nonvolatile memory structure with high speed high bandwidth and low voltage

#413
20050099836
2005-05-12

Isolation device over field in a memory device

#414
20050094461
2005-05-05

Integrated semiconductor memory

#415
20050057987
2005-03-17

Semiconductor device having read and write operations corresponding to read and write row control signals

#416
20050052917
2005-03-10

Column read amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)

#417
20050047237
2005-03-03

Data write circuit in memory system and data write method

#418
20050036386
2005-02-17

Method and apparatus for synchronization of row and column access operations

#419
20050030831
2005-02-10

Hardware and software programmable fuses for memory repair

#420
20050030798
2005-02-10

Semiconductor device and method for controlling the same

#421
20050024959
2005-02-03

Semiconductor memory device capable of relieving defective cell

#422
20050018511
2005-01-27

Semiconductor memory device which selectively controls a local input/output line sense amplifier

#423
20050002225
2005-01-06

Semiconductor memory device

#424
17813998
2023-02-28

Readout circuit layout structure and method of reading data

#425
17305275
2023-04-04

Map creation from hybrid data

#426
16183594
2020-03-10

Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same