APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES

BANK TO BANK DATA TRANSFER

SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF

DEVICES AND METHODS FOR A FINFET SENSE AMPLIFIER

DRAM DEVICE WITH MULTIPLE VOLTAGE DOMAINS

Sense amplifier circuit with precharge, memory device including the same and sensing method of memory device

Readout circuit layout and sense amplification circuit

Local bit select with improved fast read before write suppression

Apparatuses and methods for single-ended sense amplifiers

Bank to bank data transfer

Sense amplifier schemes for accessing memory cells

Sense amplifying circuit of semiconductor memory device for offset cancellation operation

Control method and controller of program suspending and resuming for memory

Apparatuses and methods for cache operations

Dram device with multiple voltage domains

Memory integrated circuit with local amplifier module and local read-write conversion module to improve operation speed and reduce number of data lines

Control method and controller of program suspending and resuming for memory

Sensing in floating-source memory architecture

Sense amplifier having offset cancellation

Dram data line switching control circuit and minimizing number of data line switches for power reduction

Bank to bank data transfer

Data replication

Sense amplifier having offset cancellation

Semiconductor device with memory banks and sense amplifier arrays

Semiconductor device

Sensing in floating-source memory architecture

Ferroelectric random access memory sensing scheme

Sense amplifier having offset cancellation

Longest element length determination in memory

Differential read-only memory (ROM) device

Memory array with bit-lines connected to different sub-arrays through jumper structures

Memories configured to control discharge of a control gate voltage of a transistor connected between a data line and a common source

Sense amplifier having offset cancellation

Apparatuses and methods for cache operations

Non-volatile memory device

Sense amplifier schemes for accessing memory cells

Apparatuses and methods to selectively perform logical operations

Memory array with individually trimmable sense amplifiers

Ferroelectric random access memory sensing scheme

SRAM with hierarchical bit lines in monolithic 3D integrated chips

Operation method for suppressing floating gate (FG) coupling

Semiconductor device with memory banks and sense amplifier arrays

Semiconductor device for compensating offset of sense amplifier

Sense amplifier having offset cancellation

Sensing in floating source string NOR architecture

Charge pump circuit with low reverse current and low peak current

Converged memory device and method thereof

Mitigating write disturbance in dual port 8T SRAM

Invert operations using sensing circuitry

Sense-line muxing scheme

Data replication

Sense amplifier schemes for accessing memory cells

Semiconductor storage device

Bank to bank data transfer

Method, system and device for non-volatile memory device operation

Bit-line sensing for correlated electron switch elements

Longest element length determination in memory

Memory array with bit-lines connected to different sub-arrays through jumper structures

Memory device

Semiconductor memory device

Semiconductor storage device

Semiconductor device for compensating offset of sense amplifier

SENSE AMPLIFIER FOR HIGH SPEED SENSING, MEMORY APPARATUS AND SYSTEM INCLUDING THE SAME

Resistance change type memory

Read circuit of storage class memory with a read reference circuit, having same bit line parasitic parameters and same read transmission gate parasitic parameters as memory

Sense amplifier having offset cancellation

Semiconductor memory device

Write driver scheme for bit-writable memories

Electronic device

Circuit and method for reading a memory cell of a non-volatile memory device

Apparatuses and methods to selectively perform logical operations

Data shifting

Sense amplifier for high speed sensing, memory apparatus and system including the same

System and method for identification of large-data flows

Charge pump circuit with low reverse current and low peak current

Self-referenced read with offset current in a memory

Sense structure based on multiple sense amplifiers with local regulation of a biasing voltage

Apparatuses and methods for cache operations

Memory array with bit-lines connected to different sub-arrays through jumper structures

Sensing buffer, peripheral circuit, and/or memory device

Semiconductor memory device and operation method thereof for suppressing floating gate (FG) coupling

Memory unit

Sense amplifier for non-volatile memory devices and related methods

Sense amplifier circuits

Semiconductor memory device for sensing memory cell with variable resistance

Semiconductor memory device with assymetric precharge

Dynamic random access memory with pseudo differential sensing

Data shifting

Semiconductor memory device including variable resistance element

Mismatch and noise insensitive sense amplifier circuit for STT MRAM

Sense amplifier, semiconductor memory device using thereof and read method thereof

Data transmission circuit

Longest element length determination in memory

Semiconductor memory device compensating difference of bitline interconnection resistance

Current comparator and electronic device including the same

Memory device of a single-ended bitline structure including reference voltage generator

Electronic device

Sense amplifier circuit

Sense structure based on multiple sense amplifiers with local regulation of a biasing voltage

Single ended sensing circuits for signal lines

Data shifting

Sense amplifier, semiconductor memory device using thereof and read method thereof

Semiconductor memory device and driving method thereof

Ternary content addressable memory utilizing common masks and hash lookups

Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells

On-the-fly trimmable sense amplifier

Sensor amplifier, memory device comprising same, and related method of operation

Memory device and read operation method thereof

Sense amplifier with dual gate precharge and decode transistors

Memory read techniques using Miller capacitance decoupling circuit

Sense amplifier

Adaptive reference scheme for magnetic memory applications

Bit-line sense amplifier, semiconductor memory device and memory system including the same

Fast bit-line pre-charge scheme

Semiconductor memory device and method for controlling semiconductor memory device

Preventing unauthorized data extraction

Dual-port SRAM with bit line clamping

Bipolar primary sense amplifier

Memory with variable strength sense amplifier

Memory device having sensing circuitry with automatic latching of sense amplifier output node

Sense amplifier

Semiconductor memory device

Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation

Semiconductor memory apparatus

Data transmission circuit

Semiconductor memory device and driving method thereof

Reading devices for memory arrays

SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA

Semiconductor memory device

Semiconductor device

Embedded memory databus architecture

Sensing circuit

Semiconductor memory device

Random access memory controller having common column multiplexer and sense amplifier hardware

Memory architecture with redundant resources

Semiconductor device

Semiconductor device and data processing system comprising semiconductor device

Differential sense amplifier without dedicated pass-gate transistors

Three dimensional memory system with intelligent select circuit

Method and system for reading from memory cells in a memory device

Memory device and method for sensing a content of a memory cell

Semiconductor memory apparatus and data input/output method thereof

Configurable memory banks of a memory device

Read only memory device with complemenary bit line pair

Memory array and memory device

Semiconductor device and method of sensing data of the semiconductor device

Semiconductor memory devices and semiconductor memory systems

Memory device and read operation method thereof

Semiconductor memory device

DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM

Sense amplifier and semiconductor apparatus including the same

Data transfer circuit of semiconductor apparatus

Internal bypassing of memory array devices

HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM

Semiconductor device and data processing system

Semiconductor memory apparatus

Method and system for providing a magnetic field aligned spin transfer torque random access memory

Pass-gated bump sense amplifier for embedded drams

Increased DRAM-array throughput using inactive bitlines

Semiconductor device and data processing system comprising semiconductor device

Method of driving a semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array

Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same

Dynamic random access memory and method of driving dynamic random access memory

Using differential signals to read data on a single-end port

Embedded memory databus architecture

Semiconductor memory device and associated local sense amplifier

Global bit select circuit interface with false write through blocking

Semiconductor device

Semiconductor device

Bit line decoder architecture for NOR-type memory array

Robust local bit select circuitry to overcome timing mismatch

SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF

Semiconductor integrated circuit including semiconductor memory

Memory Device

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Semiconductor memory device

SEMICONDUCTOR MEMORY APPARATUS

Layout structure of bit line sense amplifiers for a semiconductor memory device

SEMICONDUCTOR MEMORY APPARATUS

DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME

Semiconductor memory device

SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT/OUTPUT METHOD THEREOF

Semiconductor memory device and data read method thereof

Semiconductor memory device comprising sensing circuits with adjacent column selectors

Semiconductor device and data processing system comprising semiconductor device

Method and system for providing a hierarchical data path for spin transfer torque random access memory

Techniques for sensing a semiconductor memory device

Semiconductor device

Semiconductor memory device

DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME

Method and apparatus for synchronization of row and column access operations

Semiconductor memory device

Semiconductor device

Method of preventing coupling noises for a non-volatile semiconductor memory device

Phase change random access memory apparatus for controlling data transmission

Semiconductor device

MULTI-BANK MEMORY

Method for mitigating imprint in a ferroelectric memory

Semiconductor memory device and driving method of the same

Semiconductor memory device capable of preventing damage to a bitline during a data masking operation

Method to improve the write speed for memory products

Thin film magnetic memory device including memory cells having a magnetic tunnel junction

MEMORY DEVICES, SYSTEMS AND METHODS USING MULTIPLE 1/N PAGE ARRAYS AND MULTIPLE WRITE/READ CIRCUITS

Semiconductor memory circuit and control method for reading data

Semiconductor memory device for compensating for operating voltage difference between near cell and far cell in consideration of cell position, and memory card and memory system including the same

Semiconductor memory device

SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE DRIVING METHOD

Semiconductor memory device adopting improved local input/output line precharging scheme

Control signal generation circuit

Method and apparatus for synchronization of row and column access operations

Embedded memory databus architecture

Semiconductor memory devices having hierarchical bit-line structures

SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF

Semiconductor memory device

Semiconductor memory device that can perform successive accesses

Memory device with propagation circuitry in each sub-array and method thereof

Memory device having a single pass-gate transistor per bitline column multiplexer coupled to latch circuitry and method thereof

Semiconductor memory device

Nonvolatile memory device using variable resistive element

Sense amplifier

Sense amplifier circuit and semiconductor memory device

One-time programmable read-only memory with a time-domain sensing scheme

Semiconductor memory device

Semiconductor memory device

Memory with shared read/write circuit

Semiconductor memory device

Semiconductor memory device and memory access method

Memory control circuit and memory accessing method

METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS

Semiconductor memory device

Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same

COLUMN SELECT SIGNAL ADJUSTING CIRCUIT CAPABLE OF REDUCING INTERFERENCE BETWEEN BIT LINES AND DATA LINES AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

Hardware and software programmable fuses for memory repair

SEMICONDUCTOR MEMORY DEVICE HAVING SHARED BIT LINE SENSE AMPLIFIER SCHEME AND DRIVING METHOD THEREOF

Phase-change random access memories capable of suppressing coupling noise during read-while-write operation

Multi-level dynamic memory device

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Single end read module for register files

Low current consumption semiconductor memory device having input/output control circuit and control method thereof

Circuit and method for controlling local data line in semiconductor memory device

Semiconductor memory device

Semiconductor memory device with sense circuit connected to sense node coupled to bit line

Memory read stability using selective precharge

Circuit and method for transmitting data stream

Method to improve the write speed for memory products

Method and apparatus for synchronization of row and column access operations

High speed array pipeline architecture

SEMICONDUCTOR DEVICE

Semiconductor memory device

Embedded memory databus architecture

Memory devices with page buffer having dual registers and method of using the same

Sense amplifier for semiconductor memory device

Semiconductor memory device

Semiconductor memory device

Semiconductor device

Semiconductor memory device

Bit line decoder architecture for NOR-type memory array

Bit line decoder architecture for NOR-type memory array

Bit line decoder architecture for nor-type memory array

Data I/O line control circuit and semiconductor integrated circuit having the same

Semiconductor memory device

Semiconductor memory device of controlling bit line sense amplifier

Bit line decoder architecture for NOR-type memory array

Semiconductor memory device

Semiconductor device

Semiconductor memory device

Transfer of non-associated information on flash memory devices

Hardware and software programmable fuses for memory repair

Semiconductor memory device for simultaneously performing read access and write access

Layout structure of bit line sense amplifiers for a semiconductor memory device

High speed array pipeline architecture

Semiconductor memory device

Semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array

Integrated circuit memory system with high speed non-volatile memory data transfer capability

Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values

Semiconductor memory device

Semiconductor memory device for sensing voltages of bit lines in high speed

Semiconductor integrated circuit and method of operating the same

Semiconductor memory device including a column decoder array

Capacitor-less DRAM circuit and method of operating the same

LOOK-UP TABLE CASCADE CIRCUIT, LOOK-UP TABLE CASCADE ARRAY CIRCUIT AND A PIPELINE CONTROL METHOD THEREOF

Thin film magnetic memory device including memory cells having a magnetic tunnel junction

Semiconductor memory device having a main amplifier equipped with a current control circuit in a burst read operation

Balanced and bi-directional bit line paths for memory arrays with programmable memory cells

Semiconductor memory device

Semiconductor device

Phase change memory comprising a low-voltage column decoder

Semiconductor memory device realizing high-speed access

Semiconductor memory device

Memory device with separate read and write gate voltage controls

Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations

SEMICONDUCTOR MEMORY DEVICE WITH COLUMN TO BE SELECTED BY BIT LINE SELECTION SIGNAL

Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same

Multi-bank memory

Non-volatile memory device

MEMORY WITH ALTERABLE COLUMN SELECTION TIME

Semiconductor device

Method and apparatus for synchronization of row and column access operations

Column decoding system for semiconductor memory devices implemented with low voltage transistors

Sense amplifier