199878 ⎘
Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells; Refreshing of dynamic cells Calibration or ate or cycle tuning
CALIBRATION CIRCUIT, MEMORY, SYSTEM AND CALIBRATION METHOD
#2APPARATUS WITH REFRESH MANAGEMENT MECHANISM
#3Maintenance Operations in a DRAM
#4DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION
#5SELF-CALIBRATION IN A MEMORY DEVICE
#6Maintenance operations in a DRAM
#7SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS
#8APPARATUS WITH REFRESH MANAGEMENT MECHANISM
#9Dynamic Refresh Rate Control
#10DRAM retention test method for dynamic error correction
#11Techniques for memory system refresh
#12Apparatus with refresh management mechanism
#13Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
#14Maintenance operations in a DRAM
#15Temperature informed memory refresh
#16SEDRAM-based stacked cache system and device and controlling method therefor
#17Dynamic refresh rate control
#18Performing an on demand refresh operation of a memory sub-system
#19Apparatus with refresh management mechanism
#20REFRESH RATE CONTROL FOR A MEMORY DEVICE
#21DRAM retention test method for dynamic error correction
#22Temperature informed memory refresh
#23Dynamic refresh rate control
#24Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
#25Dynamic refresh rate control
#26Memory devices and methods of controlling an auto-refresh operation of the memory devices
#27Temperature informed memory refresh
#28Maintenance operations in a DRAM
#29Performing an on demand refresh operation of a memory sub-system
#30Method for Retaining Data
#31Refresh rate control for a memory device
#32Temperature informed memory refresh
#33DRAM retention test method for dynamic error correction
#34Performing an on demand refresh operation of a memory sub-system
#35Temperature informed memory refresh
#36Refresh control device and memory device for latching an address randomly
#37Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
#38Memory devices and methods of controlling an auto-refresh operation of the memory devices
#39Apparatus including refresh controller controlling refresh operation responsive to data error
#40Maintenance operations in a DRAM
#41Memory device for controlling refresh operation by using cell characteristic flags
#42Memory device and control method thereof
#43Using runtime reverse engineering to optimize DRAM refresh
#44Maintenance operations in a DRAM
#45Maintenance operations in a DRAM
#46Refresh control device with plurality of oscillator circuits
#47Apparatus and methods for refreshing memory cells of a semiconductor device
#48Semiconductor device and power distribution network
#49Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
#50Semiconductor memory device performing refresh operation based on weak cell information stored in memory array region and operating method thereof
#51Refresh control device with plurality of oscillator circuits
#52Periodic ZQ calibration with traffic-based self-refresh in a multi-rank DDR system
#53DRAM retention test method for dynamic error correction
#54Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
#55Dual-range clock duty cycle corrector
#56Memory controller, storage device, information processing system, and memory controlling method
#57Dynamic bandwidth throttling of DRAM accesses for memory tracing
#58Memory management device, information processing system, and method of controlling memory management device
#59Increased refresh interval and energy efficiency in a DRAM
#60Memory device refresh commands on the fly
#61Memory device and operating method thereof
#62Maintenance operations in a DRAM
#63Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
#64Semiconductor memory device, semiconductor memory system and method for controlling self refresh cycle thereof
#65Memory refresh method and devices
#66Refresh rate adjust
#67Semiconductor package with PoP structure and refresh control method thereof
#68Memory device for controlling refresh operation by using cell characteristic flags
#69Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module
#70Method of use time management for semiconductor device and semiconductor device including use time managing circuit
#71Reduced refresh power
#72Apparatus including refresh controller controlling refresh operation responsive to data error
#73Method of operating a volatile memory device and a memory controller
#74Semiconductor memory device for controlling having different refresh operation periods for different sets of memory cells
#75Systems and methods for processing data
#76Semiconductor device having a memory and calibration circuit that adjusts output buffer impedance dependent upon auto-refresh commands
#77Increased refresh interval and energy efficiency in a DRAM
#78Semiconductor memory device
#79Semiconductor memory device and method for refreshing memory cells
#80Management of memory refresh power consumption
#81Maintenance operations in a DRAM
#82Refresh scheme for memory cells with next bit table
#83Stack position determination in memory devices configured for stacked arrangements
#84Memory controller, computing device with a memory controller, and method for calibrating data transfer of a memory system
#85Semiconductor device, method for controlling the same, and semiconductor system
#86Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
#87Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module
#88Memory device, memory system and operating method thereof
#89Memory device having adjustable refresh period and method of operating the same
#90Semiconductor memory device including refresh operations having first and second cycles
#91Memory device with over-refresh and method thereof
#92Insertion-override counter to support multiple memory refresh rates
#93Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements
#94Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements
#95Memory devices with serially connected signals for stacked arrangements
#96Pad selection in memory devices configured for stacked arrangements
#97Semiconductor device and operation method thereof
#98Dynamic random access memory and boosted voltage producer therefor
#99Memory with refresh logic to accommodate low-retention storage rows
#100Systems and methods for testing pages of data stored in a memory module
#101DRAM retention test method for dynamic error correction
#102DRAM controller for variable refresh operation timing
#103Semiconductor memory device and refresh method thereof
#104Memory device refresh commands on the fly
#105Method and apparatus for clock and data recovery
#106Apparatus, method and system to determine memory access command timing based on error detection
#107Managing errors in a DRAM by weak cell encoding
#108Apparatus and method for hidden-refresh modification
#109Semiconductor memory device
#110Volatile memory device and a memory controller
#111Semiconductor memory device and method for refreshing memory cells
#112Memory refresh method and devices
#113Semiconductor device, method for controlling the same, and semiconductor system
#114Semiconductor memory device changing refresh interval depending on temperature
#115Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method thereof
#116Memory system with dynamic refreshing
#117Semiconductor device and data processing system with coordinated calibration and refresh operations
#118Memory device having reconfigurable refresh timing
#119Fully-buffered dual in-line memory module with fault correction
#120Semiconductor memory device having improved refresh characteristics
#121Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
#122Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices
#123Hidden refresh method and operating method for pseudo SRAM
#124Digit line comparison circuits
#125Variable memory refresh devices and methods
#126Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes
#127System and method for hidden refresh rate modification
#128Memory system with a programmable refresh cycle
#129Memory device refresh commands on the fly
#130Dynamic random access memory and boosted voltage producer therefor
#131PERIODIC SIGNAL GENERATING CIRCUIT DEPENDENT UPON TEMPERATURE FOR ESTABLISHING A TEMPERATURE INDEPENDENT REFRESH FREQUENCY
#132Semiconductor memory device with optimum refresh cycle according to temperature variation
#133Maintenance operations in a DRAM
#134Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
#135Dynamic random access memory (DRAM) refresh
#136Semiconductor Memory Device Suitable for Mounting on a Portable Terminal
#137Variable memory refresh devices and methods
#138Method and system for minimizing impact of refresh operations on volatile memory performance
#139Semiconductor memory device changing refresh interval depending on temperature
#140Digit line comparison circuits
#141DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF
#142Semiconductor memory device and system including the same
#143Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes
#144Memory refresh system and operating method thereof
#145Semiconductor memory device and data processing system
#146Row address code selection based on locations of substandard memory cells
#147Semiconductor device having a memory and calibration circuit that selectively adjusts an impedance of an output buffer dependent upon refresh commands
#148Fully-buffered dual in-line memory module with fault correction
#149Fully-buffered dual in-line memory module with fault correction
#150Semiconductor memory device and access method
#151Semiconductor memory and system
#152Method of estimating self refresh period of semiconductor memory device
#153Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
#154Semiconductor memory device, refresh control method thereof, and test method thereof
#155Buffer control circuit of memory device
#156Dynamic random access memory (DRAM) refresh
#157Semiconductor device, method for controlling the same, and semiconductor system
#158Self refresh operation of semiconductor memory device
#159Self refresh operation of semiconductor memory device
#160Semiconductor memory device and method of controlling auto-refresh
#161Information processing device including a plurality of cells to store data, storage control device that controls a storage section including a plurality of cells to store data, and storage control method of controlling a refresh operation of a storage section including a plurality of cells to store data
#162Information processing system
#163Variable memory refresh devices and methods
#164Apparatus and method for self-refreshing dynamic random access memory cells
#165Self-refresh based power saving circuit and method
#166Impedance calibration period setting circuit and semiconductor integrated circuit
#167Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
#168Periodic signal generating circuit dependent upon temperature for establishing a temperature independent refresh frequency
#169Memory refreshing circuit and method for memory refresh
#170Method and apparatus for performing internal hidden refreshes while latching read/write commands, address and data information for later operation
#171Method and system for controlling refresh to avoid memory cell data losses
#172Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
#173Circuit and method for controlling self-refresh cycle
#174Voltage regulator circuit for a memory circuit
#175Memory controller with refresh logic to accommodate low-retention storage rows in a memory device
#176Memory device including a programmable resistance element
#177Systems, methods, and apparatuses to save memory self-refresh power
#178Semiconductor memory device with temperature sensing device and operation thereof
#179System and method for hidden-refresh rate modification
#180Semiconductor memory device and refresh period controlling method
#181Thermal code transmission circuit and semiconductor memory device using the same
#182Dynamic random access memory device and method of determining refresh cycle thereof
#183Dynamic random access memory with low-power refresh
#184Semiconductor memory device which delays refreshment signal for performing self-refreshment
#185Refresh period signal generator with digital temperature information generation function
#186RANDOM ACCESS MEMORY AND DATA REFRESHING METHOD THEREOF
#187Method of refreshing data in a storage location based on heat dissipation level and system thereof
#188Method and apparatus for idle cycle refresh request in DRAM
#189MEMORY CONTROL DEVICE
#190Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
#191Apparatus and method for self-refreshing dynamic random access memory cells
#192Semiconductor memory device suitable for mounting on portable terminal
#193Memory control apparatus, memory control method, and computer program with refresh commands at optimum intervals
#194Memory device with self refresh cycle control function
#195Dynamic random access memory and boosted voltage producer therefor
#196Method for hiding a refresh in a pseudo-static memory
#197Buffer control circuit of memory device
#198Semiconductor memory device changing refresh interval depending on temperature
#199Circuit and method for controlling refresh periods in semiconductor memory devices
#200Semiconductor memory device changing refresh interval depending on temperature
#201Semiconductor memory, test method of semiconductor memory and system
#202Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same
#203Semiconductor memory device
#204Oscillation device, method of oscillation, and memory device
#205Oscillating device, method of adjusting the same and memory
#206Memory device including a programmable resistance element
#207Semiconductor memory device and driving method therefor
#208Refresh signal generator of semiconductor memory device
#209Semiconductor memory, system, and operating method of semiconductor memory
#210Test feature to improve DRAM charge retention yield
#211Temperature tracking oscillator circuit
#212Semiconductor memory and operating method of same
#213Method and system for controlling refresh to avoid memory cell data losses
#214METHOD OF REFRESHING A DYNAMIC RANDOM ACCESS MEMORY AND CORRESPONDING DYNAMIC RANDOM ACCESS MEMORY DEVICE, IN PARTICULAR INCORPORATED INTO A CELLULAR MOBILE TELEPHONE
#215Semiconductor memory device suitable for mounting on portable terminal
#216Refresh period adjustment technique for dynamic random access memories (DRAM) and integrated circuit devices incorporating embedded DRAM
#217Circuit and method for selecting test self-refresh period of semiconductor memory device
#218Refresh sequence control for multiple memory elements
#219Semiconductor memory device having complete hidden refresh function
#220Apparatus and method for self-refreshing dynamic random access memory cells
#221Dynamic memory refresh configurations and leakage control methods
#222METHOD OF REFRESHING DYNAMIC RANDOM ACCESS MEMORY, IN PARTICULAR IN STANDBY MODE AND IN ACTIVE OPERATING MODE, AND CORRESPONDING DYNAMIC RANDOM ACCESS MEMORY DEVICE, FOR EXAMPLE INCORPORATED INTO A CELLULAR MOBILE TELEPHONE
#223Semiconductor memory device
#224Method and system for controlling refresh to avoid memory cell data losses
#225Apparatus and method for controlling refresh operation of semiconductor integrated circuit
#226Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
#227Integrated semiconductor memory and method for operating an integrated semiconductor memory
#228Refresh control circuit in semiconductor memory apparatus and method of controlling period of refresh signal using the same
#229Semiconductor memory
#230Circuit and method for controlling self-refresh cycle
#231Semiconductor memory and refresh cycle control method
#232Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
#233Integrated Semiconductor Memory with Refreshing of Memory Cells
#234Self refresh operation of semiconductor memory device
#235Semiconductor memory device which controls refresh of a memory array in normal operation
#236Semiconductor memory device with temperature sensing device and operation thereof
#237Apparatus and method of detecting refresh cycle of semiconductor memory
#238Semiconductor storage device and refresh control method therefor
#239Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory
#240Non-skipping auto-refresh in a DRAM
#241Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
#242Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
#243Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
#244Method and system for low power refresh of dynamic random access memories
#245Method for low power refresh of a dynamic random access memory using a slower refresh rate than a normal refresh rate
#246Device and method for controlling refresh rate of memory
#247Apparatus and method for self-refreshing dynamic random access memory cells
#248Fully-buffered dual in-line memory module with fault correction
#249Fully-buffered dual in-line memory module with fault correction
#250Fully-buffered dual in-line memory module with fault correction
#251Fully-buffered dual in-line memory module with fault correction
#252Semiconductor memory device, refresh control method thereof, and test method thereof
#253Mechanism for self refresh during advanced configuration and power interface (ACPI) standard C0 power state
#254Semiconductor memory device changing refresh interval depending on temperature
#255Memory Device Having a Configurable Oscillator for Refresh Operation
#256Semiconductor device
#257Multi-chip package sharing temperature-compensated self-refresh signal and method thereof
#258Semiconductor memory device
#259Dynamic random access memory device and associated refresh cycle
#260Register read for volatile memory
#261Semiconductor memory device for achieving high reliability without increasing process complexity and cost
#262Apparatus and method for controlling refresh of semiconductor memory device according to positional information of memory chips
#263Semiconductor storage device and refresh control method therefor
#264Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same
#265Memory device with self refresh cycle control function
#266Method and apparatus for obtaining memory status information cross-reference to related applications
#267Memory with refresh cycle donation to accommodate low-retention-storage rows
#268Memory with address-differentiated refresh rate to accommodate low-retention storage rows
#269Memory device testing to support address-differentiated refresh rates
#270Memory
#271Dram with hidden refresh
#272Semiconductor memory device
#273Semiconductor memory
#274Semiconductor memory which performs the refresh operation internally and automatically without refresh commands from the exterior
#275Electronic memory apparatus and method for operating an electronic memory apparatus
#276Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
#277System and method for hidden-refresh rate modification
#278Volatile semiconductor memory
#279Self-refresh circuit with optimized power consumption
#280Method and system for performing system-level correction of memory errors
#281Variable memory array self-refresh rates in suspend and standby modes
#282Semiconductor memory device
#283Circuit and method for selecting test self-refresh period of semiconductor memory device
#284Semiconductor memory device having complete hidden refresh function
#285Self refresh period signal generation device
#286Semiconductor storage device and operating method therefor
#287Semiconductor memory device
#288Memory circuit with automatic refresh function
#289Semiconductor memory device
#290Register read for volatile memory
#291Method and system for low power refresh of dynamic random access memories
#292Dynamic memory for a cellular terminal
#293Method and system for controlling refresh to avoid memory cell data losses
#294Method and system for controlling refresh to avoid memory cell data losses
#295Memory device
#296Method and system for controlling refresh to avoid memory cell data losses
#297Non volatile semiconductor memory device having a multi-bit cell array
#298Control circuit for refresh oscillator
#299Semiconductor memory device and refresh control method
#300Method and system for minimizing impact of refresh operations on volatile memory performance