199896 ⎘
Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to and sub-groups for features not covered by these groups; Multilevel memory programming aspects Concurrent multilevel programming of more than one cell
TWO-PART PROGRAMMING OF MEMORY CELLS
#2Apparatus and method for programming data in a non-volatile memory device
#3Two-part programming of memory cells
#4First-pass dynamic program targeting (DPT)
#5Two-part programming methods
#6First-pass dynamic program targeting (DPT)
#7First-pass dynamic program targeting (DPT)
#8Two-part programming methods
#9Concurrent copying of first and second subsets of pages from media such as SLC NAND to media such as QLC or MLC NAND for completion of copying of data
#10Apparatus configured to program memory cells using an intermediate level for multiple data states
#11Programming memories with stepped programming pulses
#12Apparatus configured to program memory cells using an intermediate level for multiple data states
#13Two-part programming methods
#14Programming memories with stepped programming pulses including inhibiting a memory cell for a portion of a programming pulse and enabling that memory cell for another portion of that programming pulse
#15Efficient data path architecture for flash devices configured to perform multi-pass programming
#16Method for writing into and reading a multi-levels EEPROM and corresponding memory device
#17Programming of nonvolatile memory with verify level dependent on memory state and programming loop count
#18Storage device including a nonvolatile memory device and a controller for controlling a write operation of the nonvolatile memory device and an operating method of the storage device
#19Two-part programming methods
#20Multi-state programming for non-volatile memory
#21Semiconductor memory device and operating method thereof
#22Auto low current programming method without verify
#23Systems and methods for reduced program disturb for 3D NAND flash
#24Programming memories with stepped programming pulses
#25Two-part programming methods
#26Method for writing into and reading a multi-levels EEPROM and corresponding memory device
#27Nonvolatile memory device having variable resistive elements and method of driving the same
#28Memory devices and operating methods for a memory device
#29Data storage device comprising nonvolatile memory chips and control method thereof
#30Parallel programming scheme in multi-bit phase change memory
#31Sensing resistance variable memory
#32Two-part programming methods
#33Programming non-volatile storage including reducing impact from other memory cells
#34Saw-shaped multi-pulse programming for program noise reduction in memory
#35Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell
#36Method and apparatus for increasing memory programming efficiency through dynamic switching of sense amplifiers
#37Method of operating memory device having page buffer
#38Sensing resistance variable memory
#39Memory device, memory system having the same, and programming method of a memory cell
#40Two-part programming methods and memories
#41RESISTANCE VARIABLE MEMORY DEVICE PROGRAMMING MULTI-BIT DATA
#42Multi-stage parallel data transfer
#43Reduced-power programming of multi-level cell (MLC) memory
#44M+L bit read column architecture for M bit memory cells
#45Sensing resistance variable memory
#46Operation of a non-volatile memory array
#47Page buffer, memory device having the page buffer and method of operating the same
#48Apparatus and method of nonvolatile memory device having three-level nonvolatile memory cells
#49Nonvolatile memory devices that include a write circuit that writes data over multiple write periods using pulses whose peaks do not coincide with each other
#50Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage
#51Semiconductor memory device and write method thereof
#52Method of improving programming precision in flash memory
#53Flash memory with improved programming precision
#54High program speed MLC memory
#55Resistance change memory device
#56Resistance change memory device
#57Systems for alternate row-based reading and writing for non-volatile memory
#58Flash memory device having single page buffer structure and related programming method
#59Method of operating a programmable resistance memory array
#60Method of operating a programmable resistance memory array
#61System and method for programming non-volatile memory during burst sequential write
#62Coarse pass and fine pass multi-level NVM programming
#63Digital signaling processing for three dimensional flash memory arrays