Patents-Review.com
ClassID:

199894 ⎘

G11C2211/562 - CPC Classification

Classification description:

Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to and sub-groups for features not covered by these groups Multilevel memory programming aspects

Sub-classes:
Recent Application in this class:
#1
20240185923
2024-06-06

TWO-PART PROGRAMMING OF MEMORY CELLS

 #2
20230146046
2023-05-11

Storage system and method for multi-cell mapping

 #3
20220115071
2022-04-14

Two-part programming of memory cells

 #4
20220108754
2022-04-07

Memory system including the semiconductor memory and a controller

 #5
20210327504
2021-10-21

Multi-level cell programming using optimized multiphase mapping with balanced gray code

 #6
20210221123
2021-07-22

Writing a nonvolatile memory to programmed levels

 #7
20210050064
2021-02-18

Memory system including the semiconductor memory and a controller

 #8
20200402585
2020-12-24

Two-part programming methods

 #9
20200327933
2020-10-15

Multi-level cell programming using optimized multiphase mapping with balanced gray code

 #10
20200194063
2020-06-18

Multi-level cell programming using optimized multiphase mapping with balanced Gray code

 #11
20190392906
2019-12-26

Memory system including the semiconductor memory and a controller

 #12
20190371401
2019-12-05

Multifunctional memory cells

 #13
20190317685
2019-10-17

Apparatuses and methods for single level cell caching

 #14
20190279689
2019-09-12

Temperature-based memory operations

 #15
20190206485
2019-07-04

Two-part programming methods

 #16
20190206452
2019-07-04

Temperature-based memory operations

 #17
20180349056
2018-12-06

Apparatuses and methods for single level cell caching

 #18
20180349055
2018-12-06

Apparatuses and methods for single level cell caching

 #19
20180225220
2018-08-09

Memory device and method of operating the same

 #20
20180158528
2018-06-07

Control logic, semiconductor memory device, and method of operating the same

 #21
20180102177
2018-04-12

3D memory with staged-level multibit programming

 #22
20180096722
2018-04-05

Two-part programming methods

 #23
20180090220
2018-03-29

Semiconductor memory device having a controller configured to execute an intervening operation after a program operation and before a verify operation for that program operation

 #24
20170310341
2017-10-26

Efficient data path architecture for flash devices configured to perform multi-pass programming

 #25
20170025170
2017-01-26

Two-part programming methods

 #26
20150262657
2015-09-17

Two-part programming methods

 #27
20150154112
2015-06-04

Batch command techniques for a data storage device

 #28
20140201600
2014-07-17

Apparatus and method for encoding data for storage in multi-level nonvolatile memory

 #29
20130201757
2013-08-08

Multi-free layer MTJ and multi-terminal read circuit with concurrent and differential sensing

 #30
20120092932
2012-04-19

Two-part programming methods

 #31
20120063193
2012-03-15

Multi-level resistance change memory

 #32
20110182104
2011-07-28

Method of implementing memristor-based multilevel memory using reference resistor array

 #33
20110182102
2011-07-28

Semiconductor memory device

 #34
20110060969
2011-03-10

Method and system for error correction in flash memory

 #35
20100124108
2010-05-20

Two-part programming methods and memories

 #36
20070171730
2007-07-26

Method and system for error correction in flash memory

 #37
16103022
2019-11-19

Multi-state memory device and method for adjusting memory state characteristics of the same

 #38
14162493
2017-01-03

Digital signaling processing for three dimensional flash memory arrays