199900 ⎘
Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to and sub-groups for features not covered by these groups Multilevel memory reading aspects
Sub-classes:Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network
#2Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network
#3Semiconductor storage device and memory system including semiconductor storage device and controller
#4Memory system including the semiconductor memory and a controller
#5Memory system including the semiconductor memory and a controller
#6Semiconductor storage device and memory system including semiconductor storage device and controller
#7Memory device and method of operating the same
#8MEMORY DEVICE AND METHOD OF OPERATING THE SAME
#9OPERATION METHOD OF NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE
#10Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network
#11Read-out techniques for multi-bit cells
#12Memory system including the semiconductor memory and a controller
#13Semiconductor storage device and memory system including semiconductor storage device and controller
#14Semiconductor memory device and method of operating the same
#15Method of reading data about memory device, method of controlling memory controller, and storage device including memory device and memory controller
#16Semiconductor storage device and memory system
#17Resistance change memory device
#18Memory device and method of operating the same
#19Tri-level DRAM sense amplifer
#20Command sequence for first read solution for memory
#21Semiconductor memory device having a controller configured to execute an intervening operation after a program operation and before a verify operation for that program operation
#22Dynamic tuning of first read countermeasures
#23Memory system having optimal threshold voltage and operating method thereof
#24Independent multi-plane read and low latency hybrid read
#25Memory device and associated controlling method
#26Batch command techniques for a data storage device
#27Nonvolatile memory apparatus, and semiconductor system and computer device using the same
#28Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same
#29Apparatus and method for encoding data for storage in multi-level nonvolatile memory
#30Multi level antifuse memory device and method of operating the same
#31Detecting codewords in solid-state storage devices
#32Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same
#33Multi-level resistance change memory
#34Method and system for error correction in flash memory
#35SENSING LIGHT AND SENSING THE STATE OF A MEMORY CELL
#36Obtaining digital image of a scene with an imager moving relative to the scene
#37Sensing light and sensing the state of a memory cell an aid of a switch controlled by a schmidt trigger
#38Method and system for error correction in flash memory
#39System handling for first read read disturb