199902 ⎘
Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to and sub-groups for features not covered by these groups; Multilevel memory reading aspects Multilevel reading using successive approximation
Adjustable read retry order based on decoding success trend
#2Memory system and method of operating the same
#3Adjustable read retry order based on decoding success trend
#4Adjustable read retry order based on decoding success trend
#5Adaptive read threshold voltage tracking with gap estimation between adjacent read threshold voltages
#6MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY COMPUTATION
#7Memory system
#8Method for writing into and reading a multi-levels EEPROM and corresponding memory device
#9Adaptive read threshold voltage tracking with gap estimation between default read threshold voltages
#10Method for writing into and reading a multi-levels EEPROM and corresponding memory device
#11Method of operating memory controller and devices including memory controller
#12Semiconductor memory having electrically erasable and programmable semiconductor memory cells
#13Semiconductor memory having electrically erasable and programmable semiconductor memory cells
#14Semiconductor memory having electrically erasable and programmable semiconductor memory cells
#15State machine sensing of memory cells
#16Phase change memory structure with multiple resistance states and methods of programming and sensing same
#17Compensating for variations in memory cell programmed state distributions
#18Semiconductor memory having electrically erasable and programmable semiconductor memory cells
#19State machine sensing of memory cells
#20Phase change memory structure with multiple resistance states and methods of programming and sensing same
#21Division-based sensing and partitioning of electronic memory
#22Resistive memory having shunted memory cells
#23Semiconductor memory having electrically erasable and programmable semiconductor memory cells
#24Semiconductor memory having electrically erasable and programmable semiconductor memory cells
#25Electrically alterable non-volatile multi-level memory device and method of operating such a device