199912 ⎘
Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to and sub-groups for features not covered by these groups; Miscellaneous aspects Multilevel memory with bit inversion arrangement
Magnetic disk apparatus and method
#2Nonvolatile memory device and memory system including nonvolatile memory device
#3Memory device and method of operating the same
#4MEMORY DEVICE AND METHOD OF OPERATING THE SAME
#5Nonvolatile memory device and memory system including nonvolatile memory device
#6Memory device and method of operating the same
#7Memory health monitoring
#8Error correction code processing and data shaping for reducing wear to a memory
#9Memory health monitoring
#10Semiconductor memory device having inverting circuit and controlling method there of
#11Adaptive data shaping in nonvolatile memory
#12Representing data using a group of multilevel memory cells
#13Exploiting phase-change memory write asymmetries to accelerate write
#14Non-volatile memory device and a method of programming such device
#15Programming memory cells dependent upon distortion estimation
#16Data modification based on matching bit patterns
#17Efficient PCMS refresh mechanism
#18Coding techniques for reducing write cycles for memory
#19Low power signaling for data transfer
#20Methods and systems for memory devices with asymmetric switching characteristics
#21Non-volatile memory device and a method of programming such device
#22Memory device and method having charge level assignments selected to minimize signal coupling
#23Endurance enhancement coding of compressible data in flash memories
#24Complementary reference method for high reliability trap-type non-volatile memory
#25Data modification based on matching bit patterns
#26Multi-level cell access buffer with dual function
#27Memory devices and methods of storing data on a memory device
#28Memory sanitation using bit-inverted data
#29Memory write error correction circuit
#30Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance
#31Memory device and method having charge level assignments selected to minimize signal coupling
#32Semiconductor memory device and method of operating the same
#33Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same
#34Memory controller and a method for writing information to a K-level memory unit
#35Multi-level cell access buffer with dual function
#36Memory controller, memory system, recording and reproducing method for memory system, and recording apparatus
#37Memory device and operation method to selectively invert data
#38Uniform coding system for a flash memory
#39Memory system and related method of programming
#40Memory system
#41MULTI-LEVEL NAND FLASH MEMORY
#42Flash memory device and flash memory programming method equalizing wear-level
#43Multiple bit per cell non volatile memory apparatus and system having polarity control and method of programming same
#44Memory device and method having charge level assignments selected to minimize signal coupling
#45Single latch data circuit in a multiple level cell non-volatile memory device
#46Complementary reference method for high reliability trap-type non-volatile memory
#47Memory devices and methods of storing data on a memory device
#48Memory controller, memory system, recording and reproducing method for memory system, and recording apparatus
#49CLOCK SYNCHRONIZED NON-VOLATILE MEMORY DEVICE
#50Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same
#51MIS-transistor-based nonvolatile memory for multilevel data storage
#52Multi-level cell access buffer with dual function
#53Systems, methods and computer program products for encoding data to be written to a nonvolatile memory based on wear-leveling information
#54Semiconductor memory device and semiconductor memory system
#55Two cell per bit phase change memory
#56Apparatuses and methods for multi-bit programming
#57INTEGRATED CIRCUIT INCLUDING A MEMORY HAVING A DATA INVERSION CIRCUIT
#58Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling
#59Nonvolatile semiconductor storage device capable of high-speed writing
#60Methods of operating multi-bit flash memory devices and related systems
#61Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages
#62Multi-level cell access buffer with dual function
#63Control circuit of flash memory device and method of operating the flash memory device
#64Single latch data circuit in a multiple level call non-volatile memory device
#658/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory
#66Memory data inversion architecture for minimizing power consumption
#67Apparatus and method for writing data to phase-change memory by using power calculation and data inversion
#68Multi-bit resistive memory
#69Semiconductor memory device and method for reducing cell activation during write operations
#70Performance or power-optimized code/data storage for nonvolatile memories
#71Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling
#72Method of avoiding errors in flash memory
#73Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range
#74Clock synchronized non-volatile memory device
#75NAND type flash memory
#76Integrated circuit including resistivity changing material element
#77Single latch data circuit in a multiple level cell non-volatile memory device
#78Clock synchronized non-volatile memory device
#79Multi-bits storage memory
#80Random access memory array with parity bit structure
#81Clock synchronized nonvolatile memory device
#82Clock synchronized nonvolatile memory device
#83Method for improving the read signal in a memory having passive memory elements