ANALOG COMPUTING UNIT FOR REPRESENTING NEGATIVE WEIGHTS

MEMORY DEVICE AND METHOD OF OPERATION

ERASING OF A WORD OR A PAGE OF NON-VOLATILE MEMORY CELLS IN AN ANALOG NEURAL MEMORY SYSTEM

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

Programming of a Selected Non-volatile Memory Cell by Changing Programming Pulse Characteristics

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

Multiple row programming operation in artificial neural network array

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

PROGRAMMING OF A SELECTED NON-VOLATILE MEMORY CELL

MEMORY DEVICE AND METHOD OF OPERATION

Negative voltage switching device and non-volatile memory device using the same

Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells

NON-VOLATILE MEMORY CELL ARRAY FORMED IN A P-WELL IN A DEEP N-WELL IN A P-SUBSTRATE

Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system

Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system

Nonvolatile memory device including erase transistors

Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network

Memory device comprising source line coupled to multiple memory cells and method of operation

NOR memory cell with vertical floating gate

Non-volatile memory system using strap cells in source line pull down circuits

Precision tuning of a page or word of non-volatile memory cells and associated high voltage circuits for an analog neural memory array in an artificial neural network

Precise programming method and apparatus for analog neural memory in an artificial neural network

Four gate, split-gate flash memory array with byte erase operation

Method for determining a proper program voltage for a plurality of memory cells

Offset cancellation voltage latch sense amplifier for non-volatile memory

NOR memory cell with vertical floating gate

Non-volatile memory device

OUTPUT ARRAY NEURON CONVERSION AND CALIBRATION FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Configurable input blocks and output blocks and physical layout for analog neural memory in deep learning artificial neural network

Erasable programmable non-volatile memory

Semiconductor device and manufacturing method thereof

Three-dimensional semiconductor memory devices and method of manufacturing the same

Multi-time programming non-volatile memory

Erasable programmable non-volatile memory including two floating gate transistors with the same floating gate

Method and apparatus for configuring array columns and rows for accessing flash memory cells

Single-poly nonvolatile memory unit

MEMORIES WITH SOURCE DIFFUSIONS ELECTRICALLY COUPLED TO SOURCE-CONTACTED LAYERS

Memory cell with a flat-topped floating gate structure

Non-volatile memory device and method for controlling the non-volatile memory device

Flash memory system using negative high voltage level shifter

Flash memory device and method of programming the same

NOR memory cell with vertical floating gate

NOR memory cell with L-shaped floating gate

Semiconductor device and manufacturing method thereof

Sensing amplifier comprising fully depleted silicon-on-insulator transistors for reading a selected flash memory cell in an array of flash memory cells

Method and apparatus for configuring array columns and rows for accessing flash memory cells

Method and apparatus for configuring array columns and rows for accessing flash memory cells

Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems

Flash memory system using complementary voltage supplies

Flash memory with improved read performance

EEPROM memory architecture optimized for embedded memories

Self-aligned split-gate NAND flash memory and fabrication process

Self-aligned split-gate NAND flash memory and fabrication process

Memory device and method for programming the same