Delay stage-interweaved analog DLL/PLL

Integrated semiconductor memory and method for operating an integrated semiconductor memory

Method and apparatus for identifying short circuits in an integrated circuit device

Nonvolatile semiconductor memory

Method for determining programming voltage of nonvolatile memory

Ferroelectric memory

Built-in self test for memory interconnect testing

Phase controlled high speed interfaces

Latency control circuit and method of latency control

Memory devices configured to detect failure of temperature sensors thereof and methods of operating and testing same

Semiconductor device, semiconductor device testing method, and programming method

MRAM integrated circuits, MRAM circuits, and systems for testing MRAM integrated circuits

Method, system and memory controller utilizing adjustable write data delay settings

Integrated circuit buffer device

Calibration of thermal sensors for semiconductor dies

Internal voltage trimming circuit for use in semiconductor memory device and method thereof

Electronic circuit with test unit

Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods

Integrated semiconductor memory comprising at least one word line and method

Flash memory devices having a voltage trimming circuit and methods of operating the same

Test method for determining the wire configuration for circuit carriers with components arranged thereon

Method and apparatus providing final test and trimming for a power supply controller

Test system and method for testing a circuit

Method for testing the serviceability of bit lines in a DRAM memory device

Low voltage programmable eFuse with differential sensing scheme

Memory module with termination component

Semiconductor memory device having the operating voltage of the memory cell controlled

Drift tracking feedback for communication channels

Clock-synchronous semiconductor memory device

Delay stage-interweaved analog DLL/PLL

Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device

Semiconductor memory

Method of reducing disturbs in non-volatile memory

Memory device trims

Semiconductor memory device for performing refresh operation

Adaptive algorithm for MRAM manufacturing

Refresh-free dynamic semiconductor memory device

Low cost high density rectifier matrix memory

Memory having variable refresh control and method therefor

Memory module with termination component

Operating temperature optimization in a ferroelectric or electret memory

Housing for a semiconductor device and semiconductor device testing system for testing the contacting for semiconductor devices positioned one above the other

Memory system and test method therefor

Providing current for phase change memories

Apparatus for generating internal voltage in test mode and its method

Internal signal test device and method thereof

System and method for an asynchronous data buffer having buffer write and read pointers

Adjustable timing circuit of an integrated circuit

Semiconductor memory device

Circuits and methods of temperature compensation for refresh oscillator

Monitoring VRM-induced memory errors

Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells

On-chip EE-PROM programming waveform generation

Circuits and methods of temperature compensation for refresh oscillator

Interpolator testing system

Semiconductor memory device

Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature

Memory device

Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit

Semiconductor memory device and method for adjusting internal voltage thereof

Test method and test circuit for electronic device

System for testing integrated circuit devices

Communication channel calibration with nonvolatile parameter store for recovery

Semiconductor device with self refresh test mode

Adjustable timing circuit of an integrated circuit

Semiconductor integrated circuit and method of testing same

Method for detecting column fail by controlling sense amplifier of memory device

Memory device having delay locked loop

Magnetic random access memory

Trimming functional parameters in integrated circuits

Techniques for storing accurate operating current values

Semiconductor device with self refresh test mode

Boosted voltage generator

Method of detecting potential bridging effects between conducting lines in an integrated circuit

Memory device tester and method for testing reduced power states

Circuit module

Asynchronous, high-bandwidth memory component using calibrated timing elements

Semiconductor memory device having a delay circuit

Semiconductor memory device

Apparatus and method for adjusting slew rate in semiconductor memory device

Semiconductor integrated circuit

Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit

Integrated circuit

Delay detecting apparatus of delay element in semiconductor device and method thereof

Method and apparatus for low capacitance, high output impedance driver

Buffer device and method of operation in a buffer device

Testing memory access signal connections

Offset compensated sensing for magnetic random access memory

Non-volatile CMOS reference circuit

Non-volatile memory circuit and semiconductor device

Memory device for improved reference current configuration

Semiconductor storage device and method of controlling refreshing of semiconductor storage device

Method for detecting resistive-open defects in semiconductor memories

Semiconductor memory device and test method thereof

Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof

Non-volatile memory device and inspection method for non-volatile memory device

Detecting the status of an electrical fuse

Drift tracking feedback for communication channels

Memory module having an integrated circuit buffer device

System having a controller device, a buffer device and a plurality of memory devices

Semiconductor memory device provided with constant-current circuit having current trimming function

Method of timing calibration using slower data rate pattern

Non-volatile memory device conducting comparison operation

Semiconductor memory

Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory

Integrated circuit buffer device

Memory module with testing logic

Custom logic BIST for memory controller

Semiconductor memory device having test mode for data access time

Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy

Delay circuit having reduced power supply voltage dependency

Testing method for permanent electrical removal of an intergrated circuit output after packaging

Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM

Bias voltage applying circuit and semiconductor memory device

Memory device with clock multiplier circuit

Bit line discharge control method and circuit for a semiconductor memory

Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell

Configurable width buffered module having switch elements

Flash array implementation with local and global bit lines

Semiconductor memory device changing refresh interval depending on temperature

Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device

Providing memory test patterns for DLL calibration

Reference current generator, and method of programming, adjusting and/or operating same

Method and apparatus for identifying short circuits in an integrated circuit device

System featuring memory modules that include an integrated circuit buffer devices

Method and device for testing a sense amp

Semiconductor integrated circuit device and bit line capacitance adjusting method using the device

System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

Semiconductor memory

Method of reducing disturbs in non-volatile memory

Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same

Semiconductor integrated circuit device and digital measuring instrument

Semiconductor memory device having the operating voltage of the memory cell controlled

Delay circuit, ferroelectric memory device and electronic equipment

Circuit for detecting negative word line voltage

Thin film magnetic memory device conducting read operation by a self-reference method

Memory system and semiconductor integrated circuit

SRAM device and a method of operating the same to reduce leakage current during a sleep mode

Semiconductor device having logic circuit and macro circuit

Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations

Method and architecture to calibrate read operations in synchronous flash memory

Magnetic memory including a sense result category between logic states

Method and apparatus for characterizing shared contacts in high-density SRAM cell design

CAM test structures and methods therefor

Semiconductor device

Method for optimizing MRAM circuit performance

Method for operating a memory device

Write driver circuit in phase change memory device and method for applying write current

Apparatus for improving stability and lock time for synchronous circuits

Semiconductor memory device capable of switching between an asynchronous normal mode and a synchronous mode and method thereof

Input/output switching arrangement for semiconductor circuits, a method for testing driver circuits in semiconductor circuits

Input switching arrangement for a semiconductor circuit and test method for unidirectional input drivers in semiconductor circuits

Pulse width adjusting circuit for use in semiconductor memory device and method therefor

Active compensation for operating point drift in MRAM write operation

Multi-sample read circuit having test mode of operation

Circuit calibrating output driving strength of DRAM and method thereof

Semiconductor memory device for controlling write recovery time

System including an integrated circuit memory device having an adjustable output voltage setting

Method of detecting errors in a priority encoder and a content addressable memory adopting the same

On chip diagnosis block with mixed redundancy

Semiconductor memory having a spare memory cell

Semiconductor device capable of readjusting a reference potential during the reliabilty test

I/O interface circuit of integrated circuit

Magnetic memory having a calibration system

Method of operation in a system having a memory device having an adjustable output voltage setting

Built-in self test for memory interconnect testing

Resistive cross point memory

Circuits and methods of temperature compensation for refresh oscillator

Voltage trimming circuit

Semiconductor device

Semiconductor integrated circuit

Testing CMOS CAM with redundancy

Phase controlled high speed interfaces

Semiconductor memory device and method for testing same

Control device including connecting device for rewriting memory region

Semiconductor device, method for testing the same and IC card

Method for operating a memory device

Semiconductor memory device having memory block configuration

Semiconductor integrated circuit device

Semiconductor memory

Semiconductor memory device including page latch circuit

FeRAM using programmable register

Semiconductor integrated circuit in which voltage down converter output can be observed as digital value and voltage down converter output voltage is adjustable

Memory integrated circuit device having self reset circuit for precharging data buses based on the detection of their discharge levels

Memory device for compensating for a clock skew causing a centering error and a method for compensating for the clock skew

System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

System featuring a master device, a buffer device and a plurality of integrated circuit memory devices

Adjustable timing circuit of an integrated circuit

Memory device having an adjustable voltage swing setting

Semiconductor memory device capable of testing data line redundancy replacement circuit

Semiconductor device having PLL-circuit

Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines

Circuit and method for configuring CAM array margin test and operation

Use of I2C programmable clock generator to enable frequency variation under BMC control

Temperature detection circuit and temperature detection method

Nanoscale wire-based sublithographic programmable logic arrays

Regulating voltages in semiconductor devices

Read/program potential generating circuit

Configurable width buffered module having splitter elements

Method and circuit for precise timing of signals in an embedded DRAM array

Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrate circuit device

Configurable width buffered module having flyby elements

Fault tolerant semiconductor system

Memory bus checking procedure

Method for measuring and compensating for skews of data transmission lines by compensating for skew by delay elements switched in response to the calculated reative skew

Semiconductor memory device with a bypass circuit for verifying the characteristics of an internal clock signal

Output driver impedance control for addressable memory devices

Apparatuses and methods for refreshing memories with redundancy

Methods and apparatus for dynamically adjusting performance of partitioned memory

Detecting short circuit between word line and source line in memory device and recovery method

Output impedance calibration for signaling

DRAM and method of operating the same

Memory device having input circuit and operating method of same

Semiconductor memory device and operating method thereof

Memory device

Electronic device and method for driving the same

Incorporating bit write capability with column interleave write enable and column redundancy steering

Multi-match error detection in content addressable memory testing

DRAM and self-refresh method

Switching conditions for resistive random access memory cells

Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block

Double data rate in parallel testing

Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions