199732 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation Detection or location of defective auxiliary circuits, e.g. defective refresh counters
Semiconductor memory device capable of effectively testing failure of data
#902Semiconductor device and memory circuit including a redundancy arrangement
#903Semiconductor memory device having memory block configuration
#904Method and apparatus for measuring device mismatches
#905Semiconductor device with delay section
#906Semiconductor integrated circuit and a method of testing the same
#907Methods and apparatus for testing delay locked loops and clock skew
#908Methods and devices for regulating the timing of control signals in integrated circuit memory devices
#909SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING A SEMICONDUCTOR DEVICE
#910Semiconductor device
#911Non-volatile semiconductor memory device having different erase pass voltages for respective memory sectors and associated erase method
#912SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT
#913Memory system and semiconductor integrated circuit
#914Semiconductor Memory
#915Dll Circuit
#916Semiconductor memory device and semiconductor device
#917REFERENCE VOLTAGE GENERATING CIRCUIT
#918Memory test engine
#919Semiconductor memory device and test method thereof
#920Semiconductor memory and refresh cycle control method
#921Speed adjustment system and method for performing the same
#922Method and apparatus for output driver calibration
#923Method and apparatus for programming flash memory
#924Serial bus controller using nonvolatile ferroelectric memory
#925Method and system for preventing noise disturbance in high speed, low power memory
#926Functional verification of synchronized signals using random delays
#927Semiconductor integrated circuit and electronic device
#928Redundancy-function-equipped semiconductor memory device made from ECC memory
#929Memory controller device having timing offset capability
#930Integrated Semiconductor Memory with a Test Function and Method for Testing an Integrated Semiconductor Memory
#931Testing CMOS ternary CAM with redundancy
#932Method and apparatus for testing the connectivity of a flash memory chip
#933Circuit and method for controlling sense amplifier of semiconductor memory apparatus
#934Data generator having stable duration from trigger arrival to data output start
#935Reduction of leakage current and program disturbs in flash memory devices
#936Semiconductor integrated circuit device and method of testing the same
#937Semiconductor device and method for testing semiconductor device
#938Program time adjustment as function of program voltage for improved programming speed in memory system
#939INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUT TEST METHOD
#940Semiconductor integrated circuit and the same checking method
#941Phase-change random access memory
#942Integrated circuit having a word line driver
#943Output buffer circuit and method with self-adaptive driving capability
#944Calibration system for writing and reading multiple states into phase change memory
#945Method and system for testing a random access memory (RAM) device having an internal cache
#946Drift tracking feedback for communication channels
#947Testing method for permanent electrical removal of an integrated circuit output
#948Memory module
#949Method and apparatus providing final test and trimming for a power supply controller
#950Delay-locked loop, integrated circuit having the same, and method of driving the same
#951Setting threshold voltages of cells in a memory block to reduce leakage in the memory block
#952Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same
#953Minimizing effects of program disturb in a memory device
#954Semiconductor memory
#955Semiconductor integrated circuit
#956Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#957Configuring flash memory
#958Write latency tracking using a delay lock loop in a synchronous DRAM
#959Memory module with independently adjustable power supply
#960Method and apparatus for an oscillator within a memory device
#961Erase operation for use in non-volatile memory
#962Setting method of chip initial state
#963Voltage reset circuits for a semiconductor memory device using option fuse circuit
#964Semiconductor memory device
#965Data input method and apparatus, and liquid crystal display device using the same
#966Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line
#967Method and apparatus to control sensing time for nonvolatile memory
#968Apparatus and method for trimming static delay of a synchronizing circuit
#969Semiconductor memory module and semiconductor memory device
#970Methods to make DRAM fully compatible with SRAM
#971Fully-buffered dual in-line memory module with fault correction
#972Fully-buffered dual in-line memory module with fault correction
#973Fully-buffered dual in-line memory module with fault correction
#974Fully-buffered dual in-line memory module with fault correction
#975METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM
#976Method for detecting error correction defects
#977Monitoring VRM-induced memory errors
#978Memory interface to bridge memory buses
#979Semiconductor memory device and method of testing the same
#980Balanced sense amplifier circuits with adjustable transistor body bias
#981Trimming of analog voltages in flash memory devices
#982Semiconductor memory device changing refresh interval depending on temperature
#983Test mode for IPP current measurement for wordline defect detection
#984Method, system, and circuit for operating a non-volatile memory array
#985Method and apparatus for generating an adaptive power supply voltage
#986Method for calibrating a driver and on-die termination of a synchronous memory device
#987Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit
#988High-speed writable semiconductor memory device
#989Semiconductor leakage current detector and leakage current measurement method, semiconductor leakage current detector with voltage trimming function and reference voltage trimming method, and semiconductor integrated circuit thereof
#990Test patterns to insure read signal integrity for high speed DDR DRAM
#991Configurable MRAM and method of configuration
#992Nonvolative semiconductor memory device and operating method thereof
#993Semiconductor memory device
#994Stacked semiconductor device
#995Data input circuit of semiconductor memory device and data input method thereof
#996Semiconductor memory device comprising plural source lines
#997Semiconductor memory device with signal aligning circuit
#998On die thermal sensor of semiconductor memory device and method thereof
#999Device for controlling on die termination
#1000Test device for on die termination
#1001Semiconductor memory device for adjusting impedance of data output driver
#1002Dynamic on-die termination launch latency reduction
#1003Polarity driven dynamic on-die termination
#1004Temperature sensing circuit, voltage generation circuit, and semiconductor storage device
#1005Semiconductor memory device having delay circuit
#1006Systems and methods for automatically eliminating imbalance between signals
#1007Testing methods of a semiconductor integrated incorporating a high-frequency receiving circuit and a demodulation circuit
#1008Alterable DC power supply circuit
#1009Current control technique
#1010Power line control circuit of semiconductor device
#1011Non-volatile memory and method with reduced source line bias errors
#1012Regulating voltages for refresh operation using flash trim bits in semiconductor memory devices
#1013Non-volatile memory and method with improved sensing
#1014Current reduction circuit of semiconductor device
#1015Redundancy circuit and semiconductor apparatus having the redundancy circuit
#1016Data input/output circuit having data inversion determination function and semiconductor memory device having the same
#1017Non-volatile memory device conducting comparison operation
#1018Testing system using configurable integrated circuit
#1019System and method for controlling timing of output signals
#1020Analog preamplifier calibration
#1021Semiconductor storage device
#1022Semiconductor device and method of testing the same
#1023Silent data corruption mitigation using error correction code with embedded signaling fault detection
#1024Drift tracking feedback for communication channels
#1025System for configuring parameters for a flash memory
#1026Method and circuit for reading fuse cells in a nonvolatile memory during power-up
#1027Semiconductor device
#1028Semiconductor integrated circuit apparatus and interface test method
#1029Method of reducing disturbs in non-volatile memory
#1030Method and system for regulating a program voltage value during multilevel memory device programming
#1031Memory device and method for operating a memory device
#1032Flash memory devices configured to be programmed using variable initial program loops and related devices
#1033Closed loop controlled reference voltage calibration circuit and method
#1034Multi-port memory device with serial input/output interface
#1035Output controller with test unit
#1036Semiconductor memory device for measuring internal voltage
#1037Method for generating adjustable MRAM timing signals
#1038Semiconductor memory device for adjusting impedance of data output driver
#1039Adjustable Current Source for an MRAM Circuit
#1040Random access memory including first and second voltage sources
#1041Semiconductor memory device
#1042Flexible adjustment of on-die termination values in semiconductor device
#1043Testing ram address decoder for resistive open defects
#1044Semiconductor apparatus
#1045Method and apparatus for evaluating and optimizing a signaling system
#1046Fuse trimming circuit
#1047Semiconductor device
#1048Impedance adjusting circuit and impedance adjusting method
#1049Check testing of an address decoder
#1050Method, device and system for detecting error correction defects
#1051Semiconductor integrated circuit device
#1052Interface circuit
#1053Fuse resistance read-out circuit
#1054Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination
#1055Methods and apparatus for testing electronic circuits
#1056Integrated memory core and memory interface circuit
#1057METHOD FOR DETECTING A LEAKAGE CURRENT OF A SEMICONDUCTOR MEMORY
#1058Interface circuit and semiconductor device
#1059Configurable voltage regulator
#1060Configurable voltage regulator
#1061DRAM density enhancements
#1062Methods and systems for generating latch clock used in memory reading
#1063Methods and apparatuses for a sense amplifier
#1064Circuit for selecting a power supply voltage and semiconductor device having the same
#1065Efficient clocking scheme for ultra high-speed systems
#1066System and method for testing defects in an electronic circuit
#1067Flash memory device and method of repairing defects and trimming voltages
#1068Programmable strength output buffer for RDIMM address register
#1069System and method for testing for memory address aliasing errors
#1070System and method for testing and debugging analog circuits in a memory controller
#1071Testing of interconnects associated with memory cards
#1072Test circuitry and testing methods
#1073Delay-locked loop circuit with variable bias voltages and method of clock synchronization for a semiconductor memory device
#1074Apparatus and method for testing circuit characteristics by using eye mask
#1075Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
#1076Integrated scannable interface for testing memory
#1077Time controllable sensing scheme for sense amplifier in memory IC test
#1078Delay-lock loop and method adapting itself to operate over a wide frequency range
#1079Antifuse capacitor for configuring integrated circuits
#1080Circuitry and method for adjusting signal length
#1081Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations
#1082Method for improving stability and lock time for synchronous circuits
#1083Current reduction circuit of semiconductor device
#1084Area efficient memory architecture with decoder self test and debug capability
#1085Semiconductor memory device
#1086Antifuse circuit with dynamic current limiter
#1087Antifuse circuit with current regulator for controlling programming current
#1088Semiconductor memory
#1089ECC flag for testing on-chip error correction circuit
#1090Read source line compensation in a non-volatile memory
#1091Semiconductor device having auto trimming function for automatically adjusting voltage
#1092Delay-lock loop and method adapting itself to operate over a wide frequency range
#1093Bias voltage generator with auto trimming function
#1094Integrated circuit chip having a first delay circuit trimmed via a second delay circuit
#1095Fuse cutting test circuit, fuse cutting test method, and semiconductor circuit
#1096Delay circuit having a capacitor and having reduced power supply voltage dependency
#1097Optimized testing of on-chip error correction circuit
#1098Regulating a timing between a strobe signal and a data signal
#1099Systems and methods for maintaining performance at a reduced power
#1100Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell
#1101Method and architecture to calibrate read operations in synchronous flash memory
#1102Semiconductor device and testing method thereof
#1103On-die termination apparatus
#1104Semiconductor device, method for testing the same and IC card
#1105Memory device and method having a data bypass path to allow rapid testing and calibration
#1106Method and system for configuring parameters for flash memory
#1107Adaptive algorithm for MRAM manufacturing
#1108Adaptive algorithm for MRAM manufacturing
#1109Adaptive algorithm for MRAM manufacturing
#1110Test apparatus and test method
#1111Semiconductor integrated circuit with fuse data read circuit
#1112Internal voltage generator
#1113Memory system and semiconductor integrated circuit
#1114Internal voltage generator
#1115Semiconductor memory device with delay section
#1116Nonvolatile memory including a verify circuit
#1117Semiconductor device and method for testing semiconductor device
#1118System and method for reducing jitter of signals coupled through adjacent signal lines
#1119Circuit and method for selecting test self-refresh period of semiconductor memory device
#1120Semiconductor memory device and semiconductor device
#1121Test mode for detecting a floating word line
#1122Semiconductor device and skew adjusting method
#1123Methods and systems for generating latch clock used in memory reading
#1124Active and Passive Programming/Erasing Time and Verifiable Reading for Memory System
#1125Semiconductor memory and method for analyzing failure of semiconductor memory
#1126Detection of row-to-row shorts and other row decode defects in memory devices
#1127Programmable element latch circuit
#1128System and method for an asynchronous data buffer having buffer write and read pointers
#1129Integrated semiconductor memory having sense amplifiers selectively activated at different timing
#1130Data strobe synchronization for DRAM devices
#1131Synchronous output buffer, synchronous memory device and method of testing access time
#1132Semiconductor memory and method of storing configuration data
#1133Non-volatile memory device conducting comparison operation
#1134Memory bus checking procedure
#1135Offset compensated sensing for magnetic random access memory
#1136Semiconductor memory device and memory system using same
#1137Daisy chained multi-device system and operating method
#1138Integrated semiconductor memory with adjustable internal voltage
#1139Device and method for pulse width control in a phase change memory device
#1140Content addressable memory including a dual mode cycle boundary latch
#1141System and method for providing on-chip clock generation verification using an external clock
#1142Semiconductor integrated circuit and method of testing the same
#1143METHOD AND SYSTEM FOR DETECTING POTENTIAL RELIABILITY FAILURES OF INTEGRATED CIRCUIT
#1144Memory device with apparatus for recalibrating output signal of internal circuit and method thereof
#1145Semiconductor device
#1146Automated tests for built-in self test
#1147System, method and storage medium for providing programmable delay chains for a memory system
#1148Voltage regulator with bypass mode
#1149Serial bus controller using nonvolatile ferroelectric memory
#1150Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#1151Error test for an address decoder of a non-volatile memory
#1152Apparatus and method for bit pattern learning and computer product
#1153Multiple-time electrical fuse programming circuit
#1154Integrated semiconductor memory device with adaptation of the evaluation characteristic of sense amplifiers
#1155Output power testing apparatus for memory
#1156Integrated semiconductor memory device with test circuit for sense amplifier
#1157Thin film magnetic memory device conducting read operation by a self-reference method
#1158Method and apparatus for current sense amplifier calibration in MRAM devices
#1159On-chip self test circuit and self test method for signal distortion
#1160Techniques for storing accurate operating current values
#1161Memory modules that receive clock information and are placed in a low power state
#1162Semiconductor device having a mode of functional test
#1163System and method for testing differential signal crossover using undersampling
#1164Difference signal path test and characterization circuit
#1165Method for reading fuse information in a semiconductor memory
#1166Reading phase change memories to reduce read disturbs
#1167Apparatus and method for latency control in high frequency synchronous semiconductor device
#1168Circuits, systems and methods for dynamic reference voltage calibration
#1169Circuits, systems and methods for dynamic reference voltage calibration
#1170Leakage current management
#1171Technique for determining performance characteristics of electronic devices and systems
#1172Memory circuit having a crosstalk-glitch suppressor circuit and a control device for controlling an amount of suppression performed by the crosstalk-glitch suppressor circuit
#1173Nonvolatile semiconductor memory device using irreversible storage elements
#1174Control adjustable device configurations to induce parameter variations to control parameter skews
#1175Test validation of an integrated device
#1176Method, system and memory controller utilizing adjustable read data delay settings
#1177Reuse of functional data buffers for pattern buffers in XDR DRAM
#1178Semiconductor driver circuit with signal swing balance and enhanced testing
#1179Method, system, and circuit for operating a non-volatile memory array
#1180Method for reading non-volatile memory cells
#1181Method for reading non-volatile memory cells
#1182Semiconductor integrated circuit and a method of testing the same
#1183Techniques for storing accurate operating current values
#1184Techniques for storing accurate operating current values
#1185Integrated semiconduct memory with test circuit
#1186Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell
#1187Method and apparatus for optimizing strobe to clock relationship
#1188Method and apparatus for controlling a high voltage generator in a wafer burn-in test
#1189Method for capacitance measurement in silicon
#1190Fuse link trim algorithm for minimum residual
#1191Failure test method for split gate flash memory
#1192Method and apparatus for setting operational information of a non-volatile memory
#1193Circuitry for and method of improving statistical distribution of integrated circuits
#1194Gate dielectric antifuse circuits and methods for operating same
#1195Method for measuring offset voltage of sense amplifier and semiconductor employing the method
#1196Handling of the transmit enable signal in a dynamic random access memory controller
#1197Semiconductor integrated circuit device
#1198Delay stage-interweaved analog DLL/PLL
#1199Delay stage-interweaved analog DLL/PLL
#1200Polymer de-imprint circuit using negative voltage