199774 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details; Address generation devices; Devices for accessing memories, e.g. details of addressing circuits; Accessing single arrays Accessing multiple bits simultaneously
Memory Testing Techniques
#2SEMICONDUCTOR STORAGE APPARATUS
#3ONE-TIME PROGRAMMABLE (ROTP) NVM
#4Memory chip having on-die mirroring function and method for testing the same
#5Electronic devices including a test circuit and methods of operating the electronic devices
#6Intelligent proactive responses to operations to read data from memory cells
#7Memory device and test method thereof
#8TEST CIRCUIT AND MEMORY CHIP USING TEST CIRCUIT
#9Memory chip having on-die mirroring function and method for testing the same
#10System and method for prioritization of bit error correction attempts
#11IN-MEMORY COMPUTING DEVICE FOR 8T-SRAM MEMORY CELLS
#12Memory system and operation method thereof
#13Memory testing techniques
#14Memory system and operating method of memory system
#15Memory circuit and method of operating a memory circuit
#16Flash memory with reference voltage generation from a plurality of cells
#17Semiconductor memory device and operating method thereof
#18Integrated characterization vehicles for non-volatile memory cells
#19Safety enhancement for memory controllers
#20Content addressable memory with match hit quality indication
#21Characterizing and operating a non-volatile memory device
#22Semiconductor memory device and operating method thereof
#23Integrated circuit fault detection
#24Content addressable memory with match hit quality indication
#25Memory circuit including overlay memory cells and method of operating thereof
#26SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND OPERATING METHODS THEREOF
#27Semiconductor memory device for applying different bias voltages and operating method thereof
#28Methods of operating buffered multi-rank memory modules configured to selectively link rank control signals
#29Semiconductor apparatus with reduced risks of chip counterfeiting and network invasion
#30Memory circuit capable of being quickly written in data
#31Memory circuit with improved read and write access
#32Address translation stimuli generation for post-silicon functional validation
#33Scan compression architecture for highly compressed designs and associated methods
#34Buffered multi-rank memory modules configured to selectively link rank control signals and methods of operating the same
#35Semiconductor device, test program, and test method
#36Electronic memory device and test method of such a device
#37Scan compression architecture for highly compressed designs and associated methods
#38Semiconductor memory device, test control system, and method of operating test control system
#39Implementing ECC control for enhanced endurance and data retention of flash memories
#40Implementing ECC control for enhanced endurance and data retention of flash memories
#41Non-volatile in-memory computing device
#42Nonvolatile semiconductor memory device changing the number of selected bits and/or the number of selected bays at data write operation
#43Non-volatile memory device and method for shortened erase operation during testing
#44Semiconductor device having roll call circuit
#45Nonvolatile logic array with built-in test result signal
#46Semiconductor memory device and method of testing the same
#47Semiconductor memory device having resistive memory cells and method of testing the same
#48Test circuit and method of semiconductor memory apparatus
#49Victim port-based design for test area overhead reduction in multiport latch-based memories
#50Method and apparatus for shortened erase operation
#51Built-in test circuit and method
#52Semiconductor memory device and method of performing burn-in test on the same
#53Address output circuit and semiconductor memory device
#54Integrated circuit, test circuit, and method of testing
#55Semiconductor memory with redundant word lines, system, and method of manufacturing semiconductor memory
#56Repairing circuit for memory circuit and method thereof and memory circuit using the same
#57Using storage cells to perform computation
#58Using storage cells to perform computation
#59SEMICONDUCTOR MEMORY DEVICE PERFORMING PARALLEL TEST OPERATION
#60Using storage cells to perform computation
#61Nonvolatile semiconductor memory device
#62SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME
#63Memory block testing
#64Semiconductor memory device with signal aligning circuit
#65INTEGRATED CIRCUIT HAVING A MEMORY WITH A PLURALITY OF STORAGE CELLS OF SYNCHRONOUS DESIGN AND CONNECTED TO CLOCK GATING UNITS
#66Method of Testing an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Integrated Circuit
#67Semiconductor memory device and defect remedying method thereof
#68Synchronous semiconductor device, and inspection system and method for the same
#69Circuit and method for decoding column addresses in semiconductor memory apparatus
#70Semiconductor memory device and method thereof
#71Flash EEPROM System
#72TEST MODE MULTI-BYTE PROGRAMMING WITH INTERNAL VERIFY AND POLLING FUNCTION
#73Built in self test transport controller architecture
#74Parallel bit test circuit and method
#75Non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage
#76Semiconductor memory device capable of arbitrarily setting the number of memory cells to be tested and related test method
#77Memory block testing
#78Semiconductor memory device and defect remedying method thereof
#79At-speed multi-port memory array test method and apparatus
#80Semiconductor integrated circuit device
#81Semiconductor memory device with signal aligning circuit
#82Semiconductor memory device with reduced multi-row address testing
#83Semiconductor memory device and defect remedying method thereof
#84Non-volatile semiconductor memory device and memory system using the same
#85Method and apparatus for separating native, functional and test configurations of memory
#86Flash memory device capable of reducing test time and test method thereof
#87Flash EEprom system
#88Parallel bit testing device and method
#89Semiconductor memory device and defect remedying method thereof
#90Method for testing an integrated semiconductor memory, and integrated semiconductor memory
#91Circuit for a parallel bit test of a semiconductor memory device and method thereof
#92Synchronous semiconductor device, and inspection system and method for the same
#93Integrated memory and method for functional testing of the integrated memory
#94Method of driving and testing a semiconductor memory device
#95Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
#96Characterizing and operating a non-volatile memory device