ClassID:

199823

G11C29/814 - CPC Classification

Classification description:

Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for optimized yield

Recent Application in this class:
#1
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Semiconductor memory devices and repair methods of the semiconductor memory devices

#2
20210191829
2021-06-24

Runtime cell row replacement in a memory

#3
20200312423
2020-10-01

Memory devices having spare column remap storages and methods of remapping column addresses in the memory devices

#4
20200243159
2020-07-30

Stacked memory apparatus using error correction code and repairing method thereof

#5
20200090708
2020-03-19

Layered semiconductor device, and production method therefor

#6
20190122746
2019-04-25

On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects

#7
20190121693
2019-04-25

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them

#8
20190096505
2019-03-28

Memory devices having spare column remap storages

#9
20180197621
2018-07-12

E-fuse circuit

#10
20180129769
2018-05-10

Method and apparatus for SOC with optimal RSMA

#11
20170023863
2017-01-26

Techniques to achieve area reduction through co-optimizing logic core blocks and memory redundancies

#12
20150194201
2015-07-09

Real time correction of bit failure in resistive memory

#13
20140264251
2014-09-18

Memory cell with redundant carbon nanotube

#14
20100050135
2010-02-25

Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer

#15
20090106607
2009-04-23

Method and apparatus for SRAM macro sparing in computer chips

#16
20070266358
2007-11-15

Yield calculation method

#17
20050073875
2005-04-07

Redundancy repaired yield calculation method