199816 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
Sub-classes:SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
#2Memory device and memory system
#3Reduced footprint fuse circuit
#4Data storage apparatus and method for preventing data error using the same
#5Memory device and memory system
#6Method and apparatus for repairing memory device
#7Memory device and memory system
#8Memory having a plurality of memory cells and a plurality of word lines
#9Stacked memory having same timing domain read data and redundancy
#10Redundancy evaluation circuit for semiconductor device
#11Variable resistance memory system with redundancy lines and shielded bit lines
#12Semiconductor device, control method thereof and data processing system
#13Semiconductor memory device
#14Semiconductor device, control method thereof and data processing system
#15Semiconductor memory device having memory block configuration
#16Semiconductor memory apparatus
#17Semiconductor integrated circuit and control method
#18Nonvolatile memory device using variable resistive element
#19Semiconductor memory device having memory block configuration
#20Stacked memory device and method of repairing same
#21Nonvolatile memory device and system performing repair operation for defective memory cell
#22Semiconductor memory
#23Semiconductor memory device having memory block configuration
#24FUSE INFORMATION CONTROL DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME, AND CONTROL METHOD THEREOF
#25Stacked memory and fuse chip
#26Semiconductor memory device having memory block configuration
#27Device and method for testing integrated circuit dice in an integrated circuit module
#28Sub-array architecture memory devices and related systems and methods
#29MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF
#30Semiconductor memory device and defect remedying method thereof
#31Semiconductor memory device and redundancy method of the same
#32Method of arranging fuses in a fuse box of a semiconductor memory device and a semiconductor memory device including such an arrangement
#33Device and method having a memory array storing each bit in multiple memory cells
#34Semiconductor device and memory circuit including a redundancy arrangement
#35Semiconductor memory device having memory block configuration
#36Semiconductor memory device and defect remedying method thereof
#37Semiconductor memory device storing redundant replacement information with small occupation area
#38Semiconductor device with electrically broken fuse and its manufacture method
#39Device and method for testing integrated circuit dice in an integrated circuit module
#40Semiconductor memory device and defect remedying method thereof
#41Memory module with programmable fuse element
#42Device and method having a memory array storing each bit in multiple memory cells
#43Enhanced functionality in a two-terminal memory array
#44Semiconductor integrated circuit device
#45Semiconductor memory device
#46Method for manufacturing memory device provided with a defect recovery mechanism featuring a redundancy circuit
#47Semiconductor memory device and defect remedying method thereof
#48Integrated semiconductor memory with redundant memory cells replaceable for either true or complementary defective memory cells
#49Semiconductor device with a nonvolatile semiconductor memory circuit and a plurality of IO blocks
#50Semiconductor memory integrated circuit and layout method of the same
#51Repair fuse box of semiconductor device
#52Backside of chip implementation of redundancy fuses and contact pads
#53Semiconductor memory device having memory block configuration
#54Device having a memory array storing each bit in multiple memory cells
#55Reduced footprint fuse circuit