199376 ⎘
Arrangements for writing information into, or reading information out from, a digital store; Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers; Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
Sub-classes:Sum address memory decoded dual-read select register file
#2Semiconductor device for setting options of I/O interface circuits
#3Semiconductor storage device
#4Techniques for multi-read and multi-write of memory circuit
#5Serialized SRAM access to reduce congestion
#6Serialized SRAM access to reduce congestion
#7Strobe generation circuit and semiconductor device including the same
#8Read latency reduction in a memory device
#9Techniques for multi-read and multi-write of memory circuit
#10Semiconductor device, electronic device, data transmission method, timing controller, and vehicle
#11Serializer and memory device including the same
#12Serializer and memory device including the same
#13Preinstall of partial store cache lines
#14SYSTEMS AND METHODS FOR ADAPTIVE PARALLEL-SERIAL CONVERSION OPERATIONS
#15Pipe latch circuit which controls output of data in a read operation and data output circuit including the same
#16Serialized SRAM access to reduce congestion
#17Read latency reduction in a memory device
#18Implementing DRAM row hammer avoidance
#19Implementing DRAM row hammer avoidance
#20Parallel-serial conversion circuit for adjusting an output timing of a serial data signal with respect to a reference clock signal, and an interface circuit, a control device including the same
#21Incoming bus traffic storage system
#22LOW-POWER HIGH-SPEED DATA BUFFER
#23Data output control circuit of semiconductor apparatus
#24Information processing system, information compression device, information decompression device, information processing method, and program
#25Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure
#26Pointer based column selection techniques in non-volatile memories
#27Signal transfer apparatus and methods
#28Pipe latch circuit and driving method thereof
#29Resistance variable memory device
#30Read circuit for semiconductor memory device and semiconductor memory device
#31Synchronous flash memory with status burst output
#32Power saving sensing scheme for solid state memory
#33Double data rate-single data rate input block and method for using same
#34Signal transfer apparatus and methods
#35Power saving sensing scheme for solid state memory
#36Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure
#37Memory arrangement and method for addressing a memory
#38Synchronizer for multi-rate input data using unified first-in-first-out memory and method thereof
#39Memory decoder and data bus for burst page read
#40Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure
#41Decoder for memory data bus
#42Flash memory data bus for synchronous burst read page
#43Memory output data systems and methods with feedback
#44Power efficient read circuit for a serial output memory device and method
#45Synchronous flash memory with status burst output
#46Memory system for network broadcasting applications and method for operating the same
#47Memory device having different burst order addressing for read and write operations
#48Dual bus memory burst architecture
#49Synchronous dram system with control data
#50Semiconductor memory device and method of reading data from semiconductor memory device
#51Data output control circuit
#52Semiconductor memory device for improving access time in burst mode
#53Synchronous dynamic random access memory for burst read/write operations
#54Semiconductor memory device having a burst continuous read function
#55Apparatuses and methods for controlling wordlines and sense amplifiers
#56Apparatuses and methods for shifting data