ClassID:

199377

G11C7/1033 - CPC Classification

Classification description:

Arrangements for writing information into, or reading information out from, a digital store; Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers; Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode

Recent Application in this class:
#1
20240242744
2024-07-18

SEMICONDUCTOR MEMORY DEVICE

#2
20200349986
2020-11-05

Non-volatile memory device and storage device including the same

#3
20200194040
2020-06-18

Non-volatile memory device and storage device including the same

#4
20190096447
2019-03-28

Non-volatile memory device and storage device including the same

#5
20160203065
2016-07-14

Memory sparing on memory modules

#6
20160118089
2016-04-28

Systems and methods for maintaining memory access coherency in embedded memory blocks

#7
20160071558
2016-03-10

Memory mapping in a processor having multiple programmable units

#8
20160070664
2016-03-10

Memory mapping in a processor having multiple programmable units

#9
20160034420
2016-02-04

Memory mapping in a processor having multiple programmable units

#10
20160019178
2016-01-21

Memory mapping in a processor having multiple programmable units

#11
20150340070
2015-11-26

Line memory device and image sensor including the same

#12
20150221384
2015-08-06

Methods of operating memory devices

#13
20150049550
2015-02-19

Non-volatile memory serial core architecture

#14
20130228672
2013-09-05

Line memory device and image sensor including the same

#15
20130044543
2013-02-21

Non-volatile memory bank and page buffer therefor

#16
20130028017
2013-01-31

Determining and transferring data from a memory array

#17
20110013455
2011-01-20

Non-volatile memory bank and page buffer therefor

#18
20100214849
2010-08-26

Page buffer circuit of nonvolatile memory device and method of operating the same

#19
20100172174
2010-07-08

Semiconductor device having architecture for reducing area and semiconductor system including the same

#20
20100034039
2010-02-11

Semiconductor integrated circuit

#21
20080244303
2008-10-02

Nibble de-skew method, apparatus, and system

#22
20080123423
2008-05-29

Non-volatile memory serial core architecture

#23
20070113117
2007-05-17

Hybrid parallel/serial bus interface

#24
20070006011
2007-01-04

Nibble de-skew method, apparatus, and system

#25
20060190677
2006-08-24

Sequential nibble burst ordering for data

#26
20050250461
2005-11-10

Hybrid parallel/serial bus interface

#27
20050105370
2005-05-19

Apparatus and method for bidirectional transfer of data by a base station