207194 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AB compounds with or without impurities, e.g. doping materials; Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer Diffusion into or out of group IV semiconductors
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#2SUBSTRATE INCLUDING A PRE-EPITAXIAL STACKING FAULT EXPANSION-STOP LAYER, DEVICES INCLUDING THE SAME, AND PROCESS OF MANUFACTURE
#3VERTICAL THIN-FILM TRANSISTOR AND APPLICATION AS BIT-LINE CONNECTOR FOR 3-DIMENSIONAL MEMORY ARRAYS
#4SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
#5METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#6METHOD FOR PRODUCING A STRESS STATE IN A SEMICONDUCTIVE LAYER
#7CAPACITOR, MEMORY DEVICE, AND METHOD
#8STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH THROUGH SEMICONDUCTOR VIA
#9FinFET DEVICE AND METHODS OF FORMING THE SAME
#10Epitaxial wafer, Method of manufacturing the epitaxial wafer, and Method of manufacturing a semiconductor device using the epitaxial wafer
#11DMOS DEVICE HAVING JUNCTION FIELD PLATE AND MANUFACTURING METHOD THEREFOR
#12Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays
#13MULTIPROCESS SUBSTRATE TREATMENT FOR ENHANCED SUBSTRATE DOPING
#14Semiconductor device and a method of manufacturing a semiconductor device
#15Capacitor, memory device, and method
#16FinFET device and methods of forming the same
#17FIN FIELD-EFFECT TRANSISTOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
#18OXIDE LAYER DOPING ON A SUB CHANNEL OF A TRANSISTOR STRUCTURE
#19Lateral heterojunction bipolar transistor with emitter and/or collector regrown from substrate and method
#20Substrate processing method
#21Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array
#22Systems and Methods for Bidirectional Device Fabrication
#23Pillar-shaped semiconductor device having connection material layer for anchoring wiring conductor layer and method for producing the same
#24Method for forming semiconductor structure
#25Capacitor, memory device, and method
#26FinFET device and methods of forming the same
#27Semiconductor device and a method of manufacturing a semiconductor device
#28Integrated assemblies, and methods of forming integrated assemblies
#29Stacked connections in 3D memory and methods of making the same
#30Stacked connections in 3D memory and methods of making the same
#31Vertical transistor having bottom spacers on source/drain regions with different heights along junction region
#32Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance
#33Stacked connections in 3D memory and methods of making the same
#34Stacked connections in 3D memory and methods of making the same
#35Integrated assemblies, and methods of forming integrated assemblies
#36Semiconductor device and a method of manufacturing a semiconductor device
#37Semiconductor device and method of manufacturing the same
#38Vertical field-effect transistor devices with non-uniform thickness bottom spacers
#39Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions
#40Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays
#41Methods of doping a silicon-containing material and methods of forming a semiconductor device
#42Epitaxial wafer including boron and germanium and method of fabricating the same
#43Method of fabrication of a semiconductor device including one or more nanostructures
#44FinFET device and methods of forming the same
#45Systems and methods for bidirectional device fabrication
#46NARROW-MESA SUPER-JUNCTION MOSFET
#47Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance
#48Stacked connections in 3D memory and methods of making the same
#49Forming vertical transistor devices with greater layout flexibility and packing density
#50Space deposition between source/drain and sacrificial layers
#51FinFET semiconductor device with germanium diffusion over silicon fins
#52Pillar-shaped semiconductor device having connection material layer for anchoring wiring conductor layer and method for producing the same
#53Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement
#54Method and structure of fabricating I-shaped silicon germanium vertical field-effect transistors
#55Fin field-effect transistor having counter-doped regions between lightly doped regions and doped source/drain regions
#56Silicon carbide semiconductor device with trench gate structure and horizontally arranged channel and current spread regions
#57Fin field-effect transistor
#58METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE INCLUDING ONE OR MORE NANOSTRUCTURES
#59Semiconductor device structure and method of manufacture
#60OXIDE SEMICONDUCTOR DEVICE
#61Poly-silicon thin film and method for fabricating the same, and thin film transistor and method for fabricating the same
#62Low temperature polysilicon thin film transistor and fabricating method thereof and array substrate
#63Fabrication of strained vertical p-type field effect transistors by bottom condensation
#64Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
#65Asymmetric semiconductor device
#66Bonded substrate for epitaxial growth and method of forming the same
#67Elevationally-extending string of memory cells and methods of forming an elevationally-extending string of memory cells
#68Method for manufacturing FinFETs by implanting counter-doped regions in lightly-doped S/D extensions away from the channel
#69Composite spacer enabling uniform doping in recessed fin devices
#70Dual channel FinFETs having uniform fin heights
#71Dual channel FinFETs having uniform fin heights
#72Method for manufacturing substrate for semiconductor device
#73Low resistivity wrap-around contacts
#74Methods for forming semiconductors by diffusion
#75Methods and apparatus for preventing counter-doping during high temperature processing
#76Method, apparatus, and system having super steep retrograde well with engineered dopant profiles
#77Low resistivity wrap-around contacts
#78Fabrication of strained vertical p-type field effect transistors by bottom condensation
#79Semiconductor device and method of manufacturing semiconductor device
#80Semiconductor device and method of manufacturing the semiconductor device
#81Composite spacer enabling uniform doping in recessed fin devices
#82Method, apparatus, and system having super steep retrograde well with engineered dopant profiles
#83Method for processing a semiconductor region and an electronic device
#84Stacked nanowire devices
#85Pure boron for silicide contact
#86Pure boron for silicide contact
#87Bottom processing
#88Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins
#89Silicon-based substrate, semiconductor device, and method for manufacturing semiconductor device
#90Multi-tier replacement memory stack structure integration scheme
#91Semiconductor device and fabrication method thereof
#92Local SOI fins with multiple heights
#93Lateral bipolar transistor
#94Method of manufacturing a semiconductor device having a trench at least partially filled with a conductive material in a semiconductor substrate
#95Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs
#96Thermal processing method through light irradiation
#97Semiconductor device including dual-layer source/drain region
#98SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF
#99FinFET semiconductor device with germanium diffusion over silicon fins
#100Semiconductor device including dual-layer source/drain region
#101Structure and formation method of semiconductor device structure
#102Method for manufacturing an SGT-including semiconductor device
#103Composite spacer enabling uniform doping in recessed fin devices
#104Composite spacer enabling uniform doping in recessed fin devices
#105Method of forming semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric
#106Thin film transistor, manufacturing method thereof, array substrate, and display device
#107Pure boron for silicide contact
#108Pure boron for silicide contact
#109Extended drain MOS device for FDSOI devices
#110Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs
#111Formation of strained fins in a finFET device
#112Lateral bipolar transistor
#113FINFETs with high quality source/drain structures
#114Local SOI fins with multiple heights
#115Schottky barrier diode and method of manufacturing the same
#116Punch-through-stop after partial fin etch
#117Silicon substrates with compressive stress and methods for production of the same
#118Semiconductor device with rear-side insert structure
#119Method of manufacturing a semiconductor device having a rear-side insert structure
#120Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
#121Doping for FinFET
#122Method for FinFET device
#123METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH CONDENSED SILICON GERMANIUM LAYER
#124Formation of strained fins in a finFET device
#125Enhanced channel mobility three-dimensional memory structure and method of making thereof
#126Defects annealing and impurities activation in semiconductors at thermodynamically non-stable conditions
#127Lateral bipolar transistor
#128Substrate for semiconductor device and method of manufacturing the same
#129Method to form localized relaxed substrate by using condensation
#130Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins
#131Method of producing a semiconductor arrangement
#132Method for forming a semiconductor device and a semiconductor substrate
#133Laterally-graded doping of materials
#134Silicon-based substrate having first and second portions
#135Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs
#136Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs
#137Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins
#138SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#139Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction
#140SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
#141Semiconductor device manufacturing method
#142P-FET with graded silicon-germanium channel
#143SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD
#144Semiconductor device and method of manufacturing same
#145Semiconductor device having super-junction structures
#146Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer
#147Trench power MOSFET and manufacturing method thereof
#148Dual channel vertical field effect transistor including an embedded electrode
#149Metal replacement process for low resistance source contacts in 3D NAND
#150Multi-layer strained channel FinFET
#151Doping for FinFET
#152Semiconductor device with insert structure at a rear side and method of manufacturing
#153Semiconductor device including superlattice SiGe/Si fin structure
#154Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
#155FinFET semiconductor device with germanium diffusion over silicon fins
#156CMOS circuit and method for fabricating the same
#157SGT-including semiconductor device and method for manufacturing the same
#158PHOSPHORUS AND ARSENIC DOPING OF SEMICONDUCTOR MATERIALS
#159Conformal doping for FinFET devices
#160POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A POWER SEMICONDUCTOR DEVICE
#161Semiconductor device and method for manufacturing semiconductor device
#162Semiconductor device including a trench in a semiconductor substrate and method of manufacturing a semiconductor device
#163Process for contact doping
#164JFET device structures and methods for fabricating the same
#165Semiconductor arrangement
#166METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#167Formation of shallow junctions by diffusion from a dielectronic doped by cluster or molecular ion beams
#168SEMICONDUCTOR INTEGRATED CIRCUIT
#169Trench gate MOSFET and method of manufacturing the same
#170JFET device structures and methods for fabricating the same
#171METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
#172Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams
#173Method for producing annealed wafer and annealed wafer
#174Drain/source extension structure of a field effect transistor with reduced boron diffusion
#175Semiconductor article and method for manufacturing the same
#176Zener diode and method for fabricating the same
#177Nanosheet electrostatic discharge structure
#178Mass production process of high voltage and high current Schottky diode with diffused design
#179Pure boron for silicide contact
#180Asymmetric multi-gate FinFET
#181Methods for selectively forming a layer of increased dopant concentration
#182Pure boron for silicide contact
#183Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region
#184Integrated formation of Si and SiGe fins
#185Semiconductor substrate with multiple SiGe regions having different germanium concentrations by a single epitaxy process