207288 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups -; Conductive parts Wire-like parts or pins
Sub-classes:STACKED DIE SEMICONDUCTOR PACKAGE INCLUDING AN ARRAY OF PILLAR STRUCTURES
#2DUAL-SIDED ROUTING IN 3D SEMICONDUCTOR SYSTEM-IN-PACKAGE STRUCTURE AND METHODS OF FORMING THE SAME
#3INTERPOSER CONNECTION STRUCTURES BASED ON WIRE BONDING
#4HEAT-DISSIPATING WIREBONDED MEMBERS ON PACKAGE SURFACES
#5PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
#6SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#7Monolithic formation of a set of interconnects below active devices
#8Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same
#9POWER STAGE PACKAGE INCLUDING FLEXIBLE CIRCUIT AND STACKED DIE
#10Heat-dissipating wirebonded members on package surfaces
#11Package comprising metal layer configured for electromagnetic interference shield and heat dissipation
#12Dual-sided routing in 3D SiP structure
#13Monolithic formation of a set of interconnects below active devices
#14Semiconductor memory structure
#15Methods and apparatus for package with interposers
#16Method for forming a semiconductor memory structure
#17Power stage package including flexible circuit and stacked die
#18Power module and method for manufacturing the same
#19Dual-sided routing in 3D SiP structure
#20Semiconductor module and manufacturing method therefor
#21Electromagnetic shielding element, and transmission line assembly and electronic structure package using the same
#22Variable pin fin construction to facilitate compliant cold plates
#23Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
#24Semiconductor vertical wire bonding structure and method
#25Elbow contact for field-effect transistor and manufacture thereof
#26Methods and apparatus for package with interposers
#27Method for fabricating a row of MOS transistors
#28Tunable hardmask for overlayer metrology contrast
#29Antenna packaging solution
#30REDISTRIBUTION SYSTEM WITH ROUTING LAYERS IN MULTI-LAYERED HOMOGENEOUS STRUCTURE AND A METHOD OF MANUFACTURING THEREOF
#31REDISTRIBUTION SYSTEM WITH DENSE PITCH AND COMPLEX CIRCUIT STRUCTURES IN MULTI-LAYERED HOMOGENEOUS STRUCTURE AND A METHOD OF MANUFACTURING THEREOF
#32Tunable hardmask for overlayer metrology contrast
#33Elbow contact for field-effect transistor and manufacture thereof
#34Antenna packaging solution
#35Semiconductor package and related methods
#36MICROELECTRONIC PACKAGE FOR WAFER-LEVEL CHIP SCALE PACKAGING WITH FAN-OUT
#37Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
#38Semiconductor device and manufacturing method thereof
#39Semiconductor device and power converter
#40Method for fabricating a row of MOS transistors
#41Compliant pin fin heat sink and methods
#42Methods and apparatus for package with interposers
#43Variable pin fin construction to facilitate compliant cold plates
#44Methods of manufacturing semiconductor devices
#45Compliant pin fin heat sink and methods
#46Method for producing a power semiconductor module
#47Microelectronic package for wafer-level chip scale packaging with fan-out
#48Method for heating a metal member, method for bonding heated metal members, and apparatus for heating a metal member
#49Methods and apparatus for package with interposers
#50Etching-before-packaging horizontal chip 3D system-level metal circuit board structure and technique thereof
#51Double-etch nanowire process
#52Pin connector structure and method
#53Semiconductor device and manufacturing method of same
#54NON-CONTIGUOUS DUMMY STRUCTURE SURROUNDING THROUGH-SUBSTRATE VIA NEAR INTEGRATED CIRCUIT WIRES
#55Power semiconductor module and method for producing a power semiconductor module
#56Bonding wire to bonding pad
#57Binding wire and semiconductor package structure using the same
#58Apparatus and methods for shielding differential signal pin pairs
#59Method of forming a wire bond having a free end
#60Double-etch nanowire process
#61Wiring structure for display device
#62TFT array substrate having metal oxide part and method for manufacturing the same and display device
#63Thin film transistor array panel and manufacturing method thereof
#64Device and method for knife coating an ink based on copper and indium
#65Semiconductor device and manufacturing method of same
#66Method for electrochemically manufacturing CuSCN nanowires
#67Package-on-package assembly with wire bonds to encapsulation surface
#68Compliant pin fin heat sink and methods
#69Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate
#70Package-on-package assembly with wire bonds to encapsulation surface
#71Thin film transistor array panel and manufacturing method thereof
#72Stacked semiconductor components having conductive interconnects
#73Methods for fabricating semiconductor components with conductive interconnects having planar surfaces
#74System for fabricating semiconductor components with conductive interconnects
#75Methods for fabricating semiconductor components with conductive interconnects
#76Semiconductor components with conductive interconnects
#77Backside method for fabricating semiconductor components with conductive interconnects