207461 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture of specific parts of devices defined in group; Making of isolation regions between components; Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
TRANSISTOR WITH MODIFIED GATE STRUCTURE
#2DUMMY COMPONENTS IN INTEGRATED CIRCUITS
#3SEMICONDUCTOR DEVICES AND METHODS OF FORMATION
#4DISPLAY DEVICE
#5SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#6STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH NANOWIRES
#7EPI HEIGHT REDUCTION FOR IMPROVED TRANSISTOR PERFORMANCE
#8SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
#9DISPLAY DEVICE
#10SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#11ISOLATION STRUCTURE AND MEMORY DEVICE
#12SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF
#13Parasitic capacitance reduction in GaN-on-silicon devices
#14MICROELECTRONIC DEVICES INCLUDING HIGH ASPECT RATIO FEATURES
#15SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
#16SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME
#17Semiconductor structure and manufacturing method thereof
#18SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
#19Semiconductor device and method of manufacturing the same
#20STACKED STAIRCASE CMOS WITH BURIED POWER RAIL
#21Display device
#22SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
#23Semiconductor device and method of manufacturing the same
#24METHOD OF FORMING SEMICONDUCTOR STRUCTURE
#25Semiconductor device
#26Methods of forming high aspect ratio features
#27AN IMPROVED SHIELDED GATE TRENCH MOSFET WITH LOW ON-RESISTANCE
#28Method for forming a trench in a first semiconductor layer of a multi-layer system
#29Method for manufacturing logic device isolation in embedded storage process
#30Load switch including back-to-back connected transistors
#31Isolation structure and manufacturing method thereof
#32Method of manufacturing trench type semiconductor device
#33Semiconductor structure and method of forming the same
#34Semiconductor structure and method of forming the same
#35SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#36Remote contacts for a trench semiconductor device and methods of manufacturing semiconductor devices
#37Semiconductor device comprising a deep trench isolation structure and a trap rich isolation structure in a substrate and a method of making the same
#38Manufacturing method of semiconductor device
#39Structure and formation method of semiconductor device structure with nanowires
#40Methods of forming high aspect ratio openings and methods of forming high aspect ratio features
#41Semiconductor device and method of manufacturing the same
#42Display device with substrate comprising an opening
#43Semiconductor structure formation
#44Method for producing a donor substrate for creating a three-dimensional integrated structure, and method for producing such an integrated structure
#45Semiconductor device package and method of manufacturing the same
#46Method of forming a bottom isolation dielectric by directional sputtering of a capping layer over a pair of stacks
#47Transistors with oxide liner in drift region
#48LOCOS with sidewall spacer for different capacitance density capacitors
#49Semiconductor device
#50Oxide isolated fin-type field-effect transistors
#51Semiconductor device and method for manufacturing same
#52Display panel with substrate comprising an opening and adjacent grooves
#53Semiconductor device
#54LOCOS with sidewall spacer for different capacitance density capacitors
#55Semiconductor device with a LOCOS trench
#56Oxide isolated fin-type field-effect transistors
#57Airgap formation in BEOL interconnect structure using sidewall image transfer
#58Method for forming strained fin channel devices
#59Method for fabricating semiconductor device comprising a deep trench isolation structure and a trap rich isolation structure in a substrate
#60Three-dimensional memory device containing dummy antenna diodes
#61Airgap formation in BEOL interconnect structure using sidewall image transfer
#62Structure and formation method of semiconductor device structure with nanowires
#63Semiconductor device and method of fabricating the same
#64Memory arrays, and methods of forming memory arrays
#65Methods of forming high aspect ratio openings and methods of forming high aspect ratio features
#66Semiconductor device comprising a deep trench isolation structure and a trap rich isolation structure in a substrate and a method of making the same
#67Memory arrays, and methods of forming memory arrays
#68SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
#69Termination design for trench superjunction power MOSFET
#70Transistors with oxide liner in drift region
#71Structure and formation method of semiconductor device structure with nanowires
#72Method for producing a buried cavity structure
#73High-side power device and manufacturing method thereof
#74HIGH-SIDE POWER DEVICE AND MANUFACTURING METHOD THEREOF
#75High-side power device and manufacturing method thereof
#76Method of forming vertical transistor device
#77Method for fabricating a curve on sidewalls of a fin-shaped structure
#78Techniques for controlling transistor sub-fin leakage
#79Stress memorization technique for strain coupling enhancement in bulk FINFET device
#80Semiconductor device having a trench type device isolation film and method for fabricating the same
#81Semiconductor device having isolation structure in well of substrate
#82Stress memorization technique for strain coupling enhancement in bulk finFET device
#83Isolated semiconductor layer over buried isolation layer
#84Isolation structure of semiconductor device
#85Method for preparing trench isolation structure
#86Reverse-blocking IGBT having a reverse-blocking edge termination structure
#87Deep trench isolations and methods of forming the same
#88Filling processes
#89Substrate processing method
#90Method of manufacturing semiconductor integrated circuit device
#91High-side power device and manufacturing method thereof
#92Stress memorization technique for strain coupling enhancement in bulk finFET device
#93Deep trench isolations and methods of forming the same
#94Isolated semiconductor layer over buried isolation layer
#95Method to form SOI fins on a bulk substrate with suspended anchoring
#96Flash memory devices
#97Method of manufacturing semiconductor integrated circuit device
#98Semiconductor device and manufacturing method
#99Integrated circuits using silicon on insulator substrates and methods of manufacturing the same
#100MEMS having a cutout section on a concave portion between a substrate and a stationary member
#101Vertical gate all around (VGAA) devices and methods of manufacturing the same
#102Method of forming an isolation structure in a well of a substrate
#103Method of forming a semiconductor device including trench termination
#1043D material modification for advanced processing
#105FinFET with buried insulator layer and method for forming
#106Isolation structure of semiconductor device
#107Method of manufacturing semiconductor integrated circuit device
#108Semiconductor device and manufacturing method
#109Finfet with oxidation-induced stress
#110FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX USING SELECTIVE EPITAXY ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION
#111Method for forming flash memory devices
#112Mems having a cutout section on concave portion of a substrate
#113Insulating trench forming method
#114Isolated semiconductor layer over buried isolation layer
#115METHODS OF FORMING SEMICONDUCTOR DEVICES, INCLUDING FORMING FIRST, SECOND, AND THIRD OXIDE LAYERS
#116Bulk semiconductor fins with self-aligned shallow trench isolation structures
#117Methods and systems for using oxidation layers to improve device surface uniformity
#118FinFET semiconductor device having increased gate height control
#119Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET
#120Air gaps between copper lines
#121Mechanisms for forming semiconductor device having isolation structure
#122Method of forming integrated circuit having modified isolation structure
#123FinFET with isolation
#124Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices
#125Trench-gate semiconductor device and method for forming the same
#126Multiple-time programming memory cells and methods for forming the same
#127Lateral double diffused metal oxide semiconductor device and manufacturing method thereof
#128NARROW DIFFUSION BREAK FOR A FIN FIELD EFFECT (FinFET) TRANSISTOR DEVICE
#129Method for manufacturing a field effect transistor of a non-planar type
#130Method of forming a semiconductor device including trench termination and trench structure therefor
#131FinFET with buried insulator layer and method for forming
#132Mechanism of forming a trench structure
#133Method of controlling threshold voltage and method of fabricating semiconductor device
#134SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#135Electric field gap device and manufacturing method
#136Bulk semiconductor fins with self-aligned shallow trench isolation structures
#137Multiple-time programming memory cells and methods for forming the same
#138Manufacturing method of semiconductor device
#139Method of forming finFET having fins of different height
#140Isolation structure of semiconductor device
#141Finfets and fin isolation structures
#142Methods of fabricating semiconductor device having shallow trench isolation (STI)
#143Termination structure with multiple embedded potential spreading capacitive for trench MOSFET and method
#144FinFET semiconductor device having increased gate height control
#145Semiconductor device and method for forming the same
#146Fabrication of localized SOI on localized thick box using selective epitaxy on bulk semiconductor substrates for photonics device integration
#147Fabrication of localized SOI on localized thick box lateral epitaxial realignment of deposited non-crystalline film on bulk semiconductor substrates for photonics device integration
#148Lighted trim assembly and perforated member therefor
#149METHOD FOR FORMING TRENCH ISOLATION
#150Method for forming trench isolation
#151Method of isolating nanowires from a substrate
#152Semiconductor device and method of manufacturing the same
#153Multiple-time programming memory cells and methods for forming the same
#154Method of fabricating dual trench isolated epitaxial diode array
#155Semiconductor device and method of manufacturing the same
#156Methods for fabricating semiconductor devices
#157Method of isolating nanowires from a substrate
#158SEMICONDUCTOR DEVICE STRUCTURE INSULATED FROM A BULK SILICON SUBSTRATE AND METHOD OF FORMING THE SAME
#159Semiconductor device and manufacturing method
#160SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
#161Isolation structure, non-volatile memory having the same, and method of fabricating the same
#162Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET and method
#163ISOLATION TRENCHES FOR SEMICONDUCTOR LAYERS
#164SYSTEM AND METHOD FOR INCREASING BREAKDOWN VOLTAGE OF LOCOS ISOLATED DEVICES
#165Semiconductor device with shallow trench isolation
#166Semiconductor constructions
#167Method of isolating nanowires from a substrate
#168Forming isolation regions for integrated circuits
#169Double trench for isolation of semiconductor devices
#170Low temperature process for polysilazane oxidation/densification
#171Semiconductor array and method for manufacturing a semiconductor array
#172Semiconductor devices having tensile and/or compressive stress and methods of manufacturing
#173Isolation structure, non-volatile memory having the same, and method of fabricating the same
#174Semiconductor array and method for manufacturing a semiconductor array
#175Semiconductor constructions, and electronic systems
#176Isolation trench processing for strain control
#177ISOLATION METHOD OF ACTIVE AREA FOR SEMICONDUCTOR DEVICE
#178METHOD FOR PRODUCING SHALLOW TRENCH ISOLATION
#179Method for manufacturing a semiconductor body with a trench and semiconductor body with a trench
#180METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
#181Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device
#182Shallow trench isolation structures and a method for forming shallow trench isolation structures
#183Method of manufacturing a capacitor deep trench and of etching a deep trench opening
#184Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
#185Method of fabricating semiconductor device
#186Semiconductor array and method for manufacturing a semiconductor array
#187Method of manufacturing a capacitor deep trench and of etching a deep trench opening
#188Shallow trench isolation structures and a method for forming shallow trench isolation structures
#189Semiconductor processing methods
#190Solid-state imaging device and its manufacturing method
#191Double trench for isolation of semiconductor devices
#192Device isolation for semiconductor devices
#193SOI device with body contact self-aligned to gate
#194Memory with self-aligned trenches for narrow gap isolation regions
#195Self-aligned trench filling for narrow gap isolation regions
#196STI structure
#197Low temperature process for polysilazane oxidation/densification
#198Method for fabricating a trench isolation structure having a high aspect ratio
#199Anchoring, by lateral oxidizing, of patterns of a thin film to prevent the dewetting phenomenon
#200Low temperature process for polysilazane oxidation/densification
#201Display device with substrate comprising an opening and adjacent grooves
#202Strained fin channel devices
#203Method of forming fine interconnection for semiconductor devices
#204Formation of isolation layers using a dry-wet-dry oxidation technique
#205Termination design for trench superjunction power MOSFET
#206Method of fabricating semiconductor device
#207Semiconductor device and method for fabricating the same
#208Semiconductor devices and methods for forming the same
#209Lateral diffused metal oxide semiconductor transistor and manufacturing method thereof
#210Method of manufacturing a reverse-blocking IGBT
#211POC process flow for conformal recess fill
#212Stress memorization technique for strain coupling enhancement in bulk finFET device
#213Systems and methods for eliminating seams in atomic layer deposition of silicon dioxide film in gap fill applications
#214FinFETs and fin isolation structures