ClassID:

209379

H01L2224/0212 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto Auxiliary members for bonding areas, e.g. spacers

Sub-classes:
Recent Application in this class:
#1
20250323191
2025-10-16

DEVICE FOR CONTROLLING TRAPPED IONS INCLUDING A SUBSTRATE MOUNTED ON AN APPLICATION BOARD

#2
20250259918
2025-08-14

ELECTRONIC MODULE

#3
20240213193
2024-06-27

DEVICE FOR CONTROLLING TRAPPED IONS

#4
20220102301
2022-03-31

Device for controlling trapped ions and method of manufacturing the same

#5
20220059478
2022-02-24

Method for fabricating semiconductor device

#6
20210134744
2021-05-06

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

#7
20200294947
2020-09-17

Electronic component

#8
20190214361
2019-07-11

Semiconductor device with protection layer surrounding a bonding pad

#9
20190139933
2019-05-09

3D Chip-on-wager-on-substrate structure with via last process

#10
20180096958
2018-04-05

Method for improving wire bonding strength of an image sensor

#11
20180012862
2018-01-11

Chip-on-wafer package and method of forming same

#12
20170365579
2017-12-21

3D chip-on-wafer-on-substrate structure with via last process

#13
20170162533
2017-06-08

Semiconductor device

#14
20160272483
2016-09-22

MEMS having a cutout section on a concave portion between a substrate and a stationary member

#15
20160247779
2016-08-25

Chip-on-wafer package and method of forming same

#16
20150325520
2015-11-12

3D chip-on-wafer-on-substrate structure with via last process

#17
20150318246
2015-11-05

Chip-on-wafer package and method of forming same

#18
20150303153
2015-10-22

Mems having a cutout section on concave portion of a substrate

#19
20140054800
2014-02-27

Method for manufacturing a metal pad structure of a die, a method for manufacturing a bond pad of a chip, a die arrangement and a chip arrangement