209471 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Manufacturing methods using a lift-off mask Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
Conductive Traces in Semiconductor Devices and Methods of Forming Same
#2SEMICONDUCTOR PACKAGES WITH AN INTERMETALLIC LAYER
#3SEMICONDUCTOR PACKAGES WITH AN INTERMETALLIC LAYER
#4METHOD FOR MANUFACTURING ALUMINUM PAD OF SEMICONDUCTOR CHIP
#5INTEGRATED DEVICE COMPRISING ELONGATED PADS
#6Conductive Traces in Semiconductor Devices and Methods of Forming Same
#7Conductive bump of a semiconductor device and fabricating method thereof cross reference to related applications
#8Patterned and planarized under-bump metallization
#9Semiconductor packages with an intermetallic layer
#10Conductive bump of a semiconductor device and fabricating method thereof
#11Conductive traces in semiconductor devices and methods of forming same
#12COLLARS FOR UNDER-BUMP METAL STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
#13Semiconductor device and method of manufacture
#14BARRIER LAYER FOR INTERCONNECTS IN 3D INTEGRATED DEVICE
#15Semiconductor device and method of manufacture
#16Bump structure and fabricating method thereof
#17Chip part and manufacturing method thereof
#18Conductive connections, structures with such connections, and methods of manufacture
#19Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
#20Method of forming a contact
#21Collars for under-bump metal structures and associated systems and methods
#22Barrier layer for interconnects in 3D integrated device
#23Conductive traces in semiconductor devices and methods of forming same
#24Semiconductor packages with an intermetallic layer
#25Semiconductor chip with patterned underbump metallization and polymer film
#26Processing of thick metal pads
#27Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel
#28Integrated device package comprising photo sensitive fill between a substrate and a die
#29Semiconductor device and an electronic device
#30Common drain semiconductor device structure and method
#31Semiconductor structure with an interconnect level having a conductive pad and metallic structure such as a base of a crackstop
#32Hybrid bonding mechanisms for semiconductor wafers
#33Conductive connections, structures with such connections, and methods of manufacture
#34Bowl-shaped solder structure
#35Semiconductor chip with patterned underbump metallization and polymer film
#36Chip stack with electrically insulating walls
#37Semiconductor device and fabricating method thereof
#38Semiconductor constructions having through-substrate interconnects
#39Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation
#40Technique for wafer-level processing of QFN packages
#41Method of forming bump structure
#42Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
#43Flip chip package structure and fabrication process thereof
#44Method for producing a structure for microelectronic device assembly
#45Hybrid bonding mechanisms for semiconductor wafers
#46Bondable top metal contacts for gallium nitride power devices
#47Method for manufacturing a metal pad structure of a die, a method for manufacturing a bond pad of a chip, a die arrangement and a chip arrangement
#48Interposer system and method
#49Semiconductor structures comprising a dielectric material having a curvilinear profile
#50CHIP CONNECTION STRUCTURE AND METHOD OF FORMING
#51Controlled solder-on-die integrations on packages and methods of assembling same
#52Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation
#53Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package
#54Techniques for wafer-level processing of QFN packages
#55Methods of forming through-substrate interconnects
#56Methods for forming a semiconductor structure
#57Semiconductor apparatus having penetration electrode and method for manufacturing the same
#58Solder bump connections
#59METHOD FOR PACKAGING A SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE
#60Method of manufacturing wafer level package
#61Bump structure and fabrication method thereof
#62STACKED WAFER MANUFACTURING METHOD
#63Wafer level package and method of manufacturing the same
#64Chip and manufacturing method and application thereof