ClassID:

209517

H01L2224/03914 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Manufacturing methods; Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts

Recent Application in this class:
#1
20250183204
2025-06-05

Semiconductor Device and Method

#2
20250118690
2025-04-10

DIELECTRIC STRUCTURE FOR HIGH SPEED INTERCONNECT AND RELIABILITY ENHANCEMENT

#3
20240387450
2024-11-21

REDISTRIBUTION STRUCTURE AND METHOD OF FORMING THE SAME

#4
20240088090
2024-03-14

Chip package structure

#5
20240014152
2024-01-11

SEMICONDUCTOR DEVICE WITH UNDER-BUMP METALLIZATION AND METHOD THEREFOR

#6
20230411318
2023-12-21

Semiconductor device and method

#7
20230187393
2023-06-15

SEMICONDUCTOR DEVICE

#8
20230057560
2023-02-23

Semiconductor device including re-distribution pads disposed at different levels and a method of manufacturing the same

#9
20220384364
2022-12-01

Chip package structure

#10
20220367409
2022-11-17

Package structure and method of fabrcating the same

#11
20220310540
2022-09-29

Silicon photonic interposer with two metal redistribution layers

#12
20220223548
2022-07-14

Semiconductor device and method

#13
20210280542
2021-09-09

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

#14
20210233879
2021-07-29

Semiconductor device

#15
20210118831
2021-04-22

Semiconductor device bonding area including fused solder film and manufacturing method

#16
20210111128
2021-04-15

Semiconductor package and method of fabricating the same

#17
20210098417
2021-04-01

Method of fabricating package structure

#18
20210005565
2021-01-07

Semiconductor device

#19
20200411468
2020-12-31

Chip package structure

#20
20200395323
2020-12-17

Semiconductor structure and method for forming the same

#21
20200098713
2020-03-26

Semiconductor device

#22
20200058601
2020-02-20

Scheme for connector site spacing and resulting structures

#23
20200020654
2020-01-16

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

#24
20190385964
2019-12-19

Semiconductor device

#25
20190341377
2019-11-07

Hollow metal pillar packaging scheme

#26
20190304938
2019-10-03

SYSTEMS AND METHODS FOR WAFER-LEVEL MANUFACTURING OF DEVICES HAVING LAND GRID ARRAY INTERFACES

#27
20190252338
2019-08-15

Semiconductor devices and semiconductor devices including a redistribution layer

#28
20190252335
2019-08-15

Bond structures and the methods of forming the same

#29
20190148344
2019-05-16

Multiple plated via arrays of different wire heights on same substrate

#30
20190139918
2019-05-09

Semiconductor device bonding area including fused solder film and manufacturing method

#31
20190067228
2019-02-28

Semiconductor device

#32
20190035741
2019-01-31

Semiconductor device and a corresponding method of manufacturing semiconductor devices

#33
20180374809
2018-12-27

Integrated circuit system with carrier construction configuration and method of manufacture thereof

#34
20180366411
2018-12-20

Semiconductor package and method of fabricating the same

#35
20180301436
2018-10-18

Multiple bond via arrays of different wire heights on a same substrate

#36
20180301429
2018-10-18

Semiconductor device

#37
20180166408
2018-06-14

Bond structures and the methods of forming the same

#38
20180122760
2018-05-03

Semiconductor device and method for manufacturing the same

#39
20180108629
2018-04-19

Semiconductor device and method of manufacturing the same

#40
20180047698
2018-02-15

Semiconductor device

#41
20180040599
2018-02-08

Hollow metal pillar packaging scheme

#42
20170373031
2017-12-28

Semiconductor device including conductive layer and conductive pillar disposed on conductive layer and method of manufacturing the same

#43
20170365534
2017-12-21

Manufacturing method of semiconductor package

#44
20170358547
2017-12-14

Semiconductor devices including conductive pillars

#45
20170330853
2017-11-16

Copper structures with intermetallic coating for integrated circuit chips

#46
20170323800
2017-11-09

Power MOSFET

#47
20170287857
2017-10-05

Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods

#48
20170278805
2017-09-28

Integrated circuit chip and integrated circuit wafer with guard ring

#49
20170271316
2017-09-21

Hollow metal pillar packaging scheme

#50
20170194274
2017-07-06

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

#51
20170179055
2017-06-22

Semiconductor structure

#52
20170103956
2017-04-13

Integrated circuit package

#53
20170077584
2017-03-16

Use of electrical power multiplication for power smoothing in power distribution

#54
20170047298
2017-02-16

Scheme for connector site spacing and resulting structures

#55
20160365324
2016-12-15

Method of manufacturing wafer level packaging including through encapsulation vias

#56
20160358874
2016-12-08

Semiconductor device

#57
20160351473
2016-12-01

Semiconductor device and method for producing semiconductor device

#58
20160336288
2016-11-17

Semiconductor device

#59
20160329290
2016-11-10

Reliable device assembly

#60
20160307835
2016-10-20

Power MOSFET and manufacturing method thereof

#61
20160240484
2016-08-18

Semiconductor device and manufacturing method of same

#62
20160225751
2016-08-04

Hollow metal pillar packaging scheme

#63
20160225731
2016-08-04

Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects

#64
20160211239
2016-07-21

Package having substrate with embedded metal trace overlapped by landing pad

#65
20160172299
2016-06-16

Integrated device package comprising photo sensitive fill between a substrate and a die

#66
20160071812
2016-03-10

Scheme for connector site spacing and resulting structures

#67
20160049390
2016-02-18

Multiple bond via arrays of different wire heights on a same substrate

#68
20150380377
2015-12-31

Multiple bond via arrays of different wire heights on a same substrate

#69
20150333023
2015-11-19

Semiconductor device having solderable and bondable electrical contact pads

#70
20150325541
2015-11-12

Semiconductor device

#71
20150262866
2015-09-17

Integrated circuit package

#72
20150255410
2015-09-10

Mechanically anchored backside C4 pad

#73
20150228597
2015-08-13

Copper post structure for wafer level chip scale package

#74
20150228575
2015-08-13

Semiconductor device

#75
20150200172
2015-07-16

Package having substrate with embedded metal trace overlapped by landing pad

#76
20150187739
2015-07-02

Chip stack with electrically insulating walls

#77
20150123145
2015-05-07

Semiconductor device and method for producing the same

#78
20150118841
2015-04-30

Semiconductor device and method for manufacturing the same

#79
20150115440
2015-04-30

Semiconductor device for use in flip-chip bonding, which reduces lateral displacement

#80
20150091164
2015-04-02

Semiconductor device

#81
20150076689
2015-03-19

Hollow metal pillar packaging scheme

#82
20150072516
2015-03-12

Method for removing electroplated metal facets and reusing a barrier layer without chemical mechanical polishing

#83
20150021765
2015-01-22

Semiconductor device

#84
20140376200
2014-12-25

Method of forming a reliable microelectronic assembly

#85
20140332954
2014-11-13

Semiconductor device

#86
20140319689
2014-10-30

Contact pads with sidewall spacers and method of making contact pads with sidewall spacers

#87
20140094006
2014-04-03

Transistor formation using cold welding

#88
20140091370
2014-04-03

Transistor formation using cold welding

#89
20140070408
2014-03-13

Plating structure for wafer level packages

#90
20140048941
2014-02-20

Contact pads with sidewall spacers and method of making contact pads with sidewall spacers

#91
20140035131
2014-02-06

Semiconductor devices having stacked solder bumps with intervening metal layers to provide electrical interconnections

#92
20140021618
2014-01-23

Semiconductor device and manufacturing method of same

#93
20130313710
2013-11-28

Semiconductor Constructions and Methods of Forming Semiconductor Constructions

#94
20130309861
2013-11-21

Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts

#95
20130256890
2013-10-03

Shallow via formation by oxidation

#96
20130256881
2013-10-03

Semiconductor device

#97
20130234319
2013-09-12

Semiconductor constructions

#98
20130234316
2013-09-12

Self-aligned polymer passivation/aluminum pad

#99
20130213702
2013-08-22

Bumping process and structure thereof

#100
20130193569
2013-08-01

Integrated Circuit Die And Method Of Fabricating

#101
20130181340
2013-07-18

Semiconductor devices with compliant interconnects

#102
20130099380
2013-04-25

WAFER LEVEL CHIP SCALE PACKAGE DEVICE AND MANUFACTURING METHOD THEROF

#103
20130049190
2013-02-28

Methods of fabricating semiconductor chip solder structures

#104
20130022830
2013-01-24

Bumping process and structure thereof

#105
20130005145
2013-01-03

Methods of forming a metal pattern

#106
20120261608
2012-10-18

Etchant and method for manufacturing semiconductor device using same

#107
20120241949
2012-09-27

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

#108
20120193793
2012-08-02

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

#109
20120161319
2012-06-28

BALL GRID ARRAY METHOD AND STRUCTURE

#110
20120146212
2012-06-14

Solder bump connections

#111
20120007230
2012-01-12

Method of forming semiconductor die

#112
20110254151
2011-10-20

Method for fabricating bump structure without UBM undercut

#113
20110210451
2011-09-01

Methods of forming a metal pattern and semiconductor device structure

#114
20110156248
2011-06-30

Semiconductor device and method for manufacturing the same

#115
20110101539
2011-05-05

Semiconductor device including bottom surface wiring and manfacturing method of the semiconductor device

#116
20110084392
2011-04-14

Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers

#117
20100248425
2010-09-30

Chip-size-package semiconductor chip and manufacturing method

#118
20100187685
2010-07-29

Semiconductor device

#119
20100081269
2010-04-01

Method for manufacturing semiconductor device having electrode for external connection

#120
20100065965
2010-03-18

Methods of forming solder connections and structure thereof

#121
20090127709
2009-05-21

Semiconductor device

#122
20090057909
2009-03-05

UNDER BUMP METALLIZATION STRUCTURE HAVING A SEED LAYER FOR ELECTROLESS NICKEL DEPOSITION

#123
20090020871
2009-01-22

SEMICONDUCTOR CHIP WITH SOLDER BUMP SUPPRESSING GROWTH OF INTER-METALLIC COMPOUND AND METHOD OF FABRICATING THE SAME

#124
20080248645
2008-10-09

Method to create a metal pattern using a damascene-like process

#125
20080164575
2008-07-10

Method for manufacturing a three-dimensional semiconductor device and a wafer used therein

#126
20080026560
2008-01-31

Methods of forming electronic structures including conductive shunt layers and related structures

#127
20080006919
2008-01-10

Flip chip package and method of fabricating the same

#128
20070287278
2007-12-13

Methods of forming solder connections and structure thereof

#129
20070246133
2007-10-25

Method for Electroplating and Contact Projection Arrangement

#130
20060252225
2006-11-09

Intermediate semiconductor device structures

#131
20060212176
2006-09-21

Use of electrical power multiplication for power smoothing in power distribution

#132
20060190513
2006-08-24

Systems and methods for power smoothing in power distribution

#133
20060009023
2006-01-12

Methods of forming electronic structures including conductive shunt layers and related structures

#134
20050242446
2005-11-03

INTEGRATED CIRCUIT PACKAGE WITH DIFFERENT HARDNESS BUMP PAD AND BUMP AND MANUFACTURING METHOD THEREFOR

#135
20050230783
2005-10-20

High performance system-on-chip discrete components using post passivation process

#136
20050170634
2005-08-04

High performance system-on-chip discrete components using post passivation process

#137
20050092611
2005-05-05

Bath and method for high rate copper deposition

#138
20050085062
2005-04-21

Processes and tools for forming lead-free alloy solder precursors

#139
20050014355
2005-01-20

Under-bump metallization layers and electroplated solder bumping technology for flip-chip

#140
16454435
2020-09-08

Chip package structure and method for forming the same