ClassID:

209542

H01L2224/05575 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area; External layer Plural external layers

Recent Application in this class:
#1
20250118714
2025-04-10

SEMICONDUCTOR PACKAGE

#2
20230282608
2023-09-07

SEMICONDUCTOR DIE PACKAGE

#3
20230238305
2023-07-27

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

#4
20220013479
2022-01-13

Method for forming conductive layer, and conductive structure and forming method therefor

#5
20210280542
2021-09-09

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

#6
20210225798
2021-07-22

Additive manufacturing of a frontside or backside interconnect of a semiconductor die

#7
20200020654
2020-01-16

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

#8
20160343688
2016-11-24

Method for fabricating semiconductor package having a multi-layer molded conductive substrate and structure

#9
20160071782
2016-03-10

Semiconductor device having multiple bonded heat sinks

#10
20160027666
2016-01-28

Two step method of rapid curing a semiconductor polymer layer

#11
20150325552
2015-11-12

Chip package and method for forming the same

#12
20150048495
2015-02-19

Adhesive for semiconductor, fluxing agent, manufacturing method for semiconductor device, and semiconductor device

#13
20150044864
2015-02-12

Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

#14
20140197533
2014-07-17

Method for manufacturing a semiconductor device having multiple heat sinks

#15
20140117535
2014-05-01

Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

#16
20110266670
2011-11-03

WAFER LEVEL CHIP SCALE PACKAGE WITH ANNULAR REINFORCEMENT STRUCTURE

#17
20070166992
2007-07-19

Method for fabricating last level copper-to-C4 connection with interfacial cap structure