ClassID:

211828

H01L2224/9201 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups  - ; Specific sequence of method steps Forming connectors during the connecting process, e.g. in-situ formation of bumps

Recent Application in this class:
#1
20250219004
2025-07-03

CONNECTING STRUCTURE

#2
20250157975
2025-05-15

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

#3
20250054898
2025-02-13

BUFFER LAYER FOR CHIPS ON WAFER SEMICONDUCTOR DEVICE ASSEMBLIES

#4
20230361073
2023-11-09

METHOD FOR MANUFACTURING WINDOW BALL GRID ARRAY (WBGA) PACKAGE

#5
20230282665
2023-09-07

Close butted collocated variable technology imaging arrays on a single ROIC

#6
20220320059
2022-10-06

Display device and method of fabricating the display device

#7
20220130883
2022-04-28

Close butted collocated variable technology imaging arrays on a single ROIC

#8
20220108973
2022-04-07

Semiconductor device assembly and method therefor

#9
20210272943
2021-09-02

Display device and method of fabricating the display device

#10
20200002162
2020-01-02

Semiconductor device packages and methods of manufacturing the same

#11
20180158757
2018-06-07

Method for electrically contacting a component by galvanic connection of an open-pored contact piece, and corresponding component module

#12
20160358886
2016-12-08

Arrangement of multiple power semiconductor chips and method of manufacturing the same

#13
20160329290
2016-11-10

Reliable device assembly

#14
20160225730
2016-08-04

Electrode connection structure and electrode connection method

#15
20150054140
2015-02-26

Stack of semiconductor structures and corresponding manufacturing method

#16
20140376200
2014-12-25

Method of forming a reliable microelectronic assembly

#17
20140328039
2014-11-06

SYSTEMS AND METHODS FOR VOID REDUCTION IN A SOLDER JOINT

#18
20140239502
2014-08-28

Electronic device comprising at least a chip enclosed in a package and a corresponding assembly process

#19
20130292823
2013-11-07

Stack of semiconductor structures and corresponding manufacturing method

#20
20120319268
2012-12-20

CONDUCTIVE CONNECTION SHEET, METHOD FOR CONNECTING TERMINALS, METHOD FOR FORMING CONNECTION TERMINAL, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

#21
20120193782
2012-08-02

Semiconductor device, method of manufacturing semiconductor device, and electronic device

#22
20110097846
2011-04-28

Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same

#23
20100203675
2010-08-12

Flip chip mounting body, flip chip mounting method and flip chip mounting apparatus

#24
20100001411
2010-01-07

Method for mutually connecting substrates, flip chip mounting body, and mutual connection structure between substrates

#25
20090085227
2009-04-02

FLIP-CHIP MOUNTING BODY AND FLIP-CHIP MOUNTING METHOD

#26
20090008800
2009-01-08

Flip chip mounting body, flip chip mounting method and flip chip mounting apparatus

#27
20080105976
2008-05-08

Metal filled through via structure for providing vertical wafer-to-wafer interconnection

#28
20080032448
2008-02-07

Semiconductor device with stacked chips and method for manufacturing thereof

#29
20070290337
2007-12-20

Electrically conductive connection, electronic component and method for their production

#30
20070287225
2007-12-13

Method of manufacturing an integrated circuit

#31
20070262468
2007-11-15

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

#32
20060251897
2006-11-09

Growth of carbon nanotubes to join surfaces

#33
20050205968
2005-09-22

Multi-chip package (MCP) with a conductive bar and method for manufacturing the same