207663 ⎘
Details of semiconductor or other solid state devices; Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
INTEGRATED CHIP HAVING A BURIED POWER RAIL
#2HEAT SLUG ATTACHED TO A DIE PAD FOR SEMICONDUCTOR PACKAGE
#3FLIP-CHIP SEMICONDUCTOR-ON-INSULATOR TRANSISTOR LAYOUT
#4FIELD-EFFECT TRANSISTORS WITH INTERLEAVED FINGER CONFIGURATION
#5ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
#6INTEGRATED CHIP HAVING A BURIED POWER RAIL
#7SEMICONDUCTOR DEVICE, AMPLIFYING DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#8Heat slug attached to a die pad for semiconductor package
#9Semiconductor device
#10Electrostatic discharge protection circuit having a metal connection and method for manufacturing the electrostatic discharge protection circuit
#11Integrated chip having a buried power rail
#12Open cavity bridge power delivery architectures and processes
#13Fabricating field-effect transistors with interleaved source and drain finger configuration
#14Flip-chip semiconductor-on-insulator transistor layout
#15Semiconductor-on-insulator transistor layout for radio frequency power amplifiers
#16Semiconductor device package and method of manufacturing the same
#17Grounding techniques for backside-biased semiconductor dice and related devices, systems and methods
#18SEMICONDUCTOR DEVICE
#19Fabricating field-effect transistors with body contacts between source, gate and drain assemblies
#20Dual bond pad structure for photonics
#21Backside contact to a final substrate
#22Backside contact to a final substrate
#23Grounding techniques for backside-biased semiconductor dice and related devices, systems and methods
#24On-chip reference electrode for biologically sensitive field effect transistor
#25Stacked field-effect transistor switch
#26Semiconductor device
#27Backside contact to a final substrate
#28Backside contact to a final substrate
#29Backside contact to a final substrate
#30Arrangement of penetrating electrode interconnections
#31Non-symmetric body contacts for field-effect transistors
#32Body contacts for field-effect transistors
#33Dual bond pad structure for photonics
#34Backside contact to a final substrate
#35Backside contact to a final substrate
#36Backside contact to final substrate
#37Insulated-gate photoconductive semiconductor switch
#38Metal layout for radio-frequency switches
#39Devices and methods related to radio-frequency switches having reduced-resistance metal layout
#40Copper interconnect structures and methods of making same
#41Flattened substrate surface for substrate bonding
#42Copper interconnect structures and methods of making same
#43Flattened substrate surface for substrate bonding
#44Pattern for improved visual inspection of semiconductor devices
#45Semiconductor device having silicon on insulator structure and method of fabricating the same
#46Semiconductor package structure and method for manufacturing the same