207912 ⎘
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier; Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
Sub-classes:CAPACITOR AND METHOD FOR FORMING THE SAME
#2MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application
#3FLEXIBLE ELECTRONIC ASSEMBLY
#4SEMICONDUCTOR CELL AND ACTIVE AREA ARRANGEMENT
#5Capacitor and method for forming the same
#6Capacitor and method for forming the same
#7Flexible electronic assembly
#8Semiconductor device structures with a substrate biasing scheme
#9MOSFET and memory cell having improved drain current through back bias application
#10Semiconductor chip state detector
#11Display assembly
#12Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
#13Ferroelectric resonator
#14MOSFET and memory cell having improved drain current through back bias application
#15Display device
#16Conductive layer structures for substrates
#17Body-bias voltage routing structures
#18CONDUCTIVE LAYER STRUCTURES FOR SUBSTRATES
#19Display device
#20Display assembly
#21Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
#22MOSFET and memory cell having improved drain current through back bias application
#23Semiconductor device performing write operation and write leveling operation
#24Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
#25Body-bias voltage routing structures
#26Semiconductor device and method for fabricating the same
#27Integrated circuit device having defined gate spacing and method of designing and fabricating thereof
#28Biasing bulk of a transistor
#29Body-bias voltage routing structures
#30Semiconductor device
#31Cross-coupled transistor circuit defined on four gate electrode tracks
#32Cross-coupled transistor circuit defined on three gate electrode tracks
#33Cross-coupled transistor circuit defined on two gate electrode tracks
#34Semiconductor device and method for fabricating the same
#35Method of fabricating a semiconductor device having a defined minimum gate spacing between adjacent gate structures
#36Semiconductor integrated circuit device
#37BIAS voltage generation circuit for an SOI radio frequency switch
#38Semiconductor integrated circuit device
#39Integrated circuit comprising a transistor and a capacitor, and fabrication method
#40Structure for spanning gap in body-bias voltage routing structure
#41Semiconductor integrated circuit device having power reduction mechanism
#42Semiconductor structures with body contacts and fabrication methods thereof
#43Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures
#44Semiconductor memory device and manufacturing method of the same
#45Semiconductor memory device and manufacturing method of the same
#46Memory structure for reduced floating body effect
#47Methods of reducing floating body effect
#48Fully integrated floating power supply for high voltage technologies including N-EPI biasing
#49Semiconductor structures with body contacts and fabrication methods thereof
#50Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures
#51Methods of reducing floating body effect
#52Semiconductor device with a cavity therein and a method of manufacturing the same
#53Semiconductor integrated circuit having interface circuit containing pull-up resistor and blocking diode, circuit module including such integrated circuit, and electronic apparatus including such circuit modules
#54Memory structure for reduced floating body effect
#55Apparatus for forming dielectric structures in integrated circuits
#56Semiconductor memory device and manufacturing method of the same
#57Semiconductor integrated circuit device having power reduction mechanism
#58Self-optimizing circuits for mitigating total ionizing dose effects, temperature drifts, and aging phenomena in fully-depleted silicon-on-insulator technologies