208009 ⎘
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Sub-classes:FRONT-SIDE-TYPE IMAGE SENSOR
#2Method for Fabricating an Asymmetric Halo-Implant Body-Source-Tied SOI Device
#3METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT
#4METHODS RELATED TO RADIO-FREQUENCY SWITCHING DEVICES HAVING IMPROVED VOLTAGE HANDLING CAPABILITY
#5SOI SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
#6RELEASE LAYER CONTAINING SEMICONDUCTOR-ON-INSULATOR SUBSTRATES
#7Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating
#8TRANSISTOR WITH TRENCH ISOLATED WELL FOR SEMICONDUCTOR DEVICE ASSEMBLIES
#9PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTAL MATERIAL
#10Distributed FET Back-Bias Network
#11NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE
#12S-Contact for SOI
#13Main-auxiliary field-effect transistor configurations
#14OPENING IN STRESS-INDUCING LINER(S) BETWEEN TRANSISTORS
#15Field Effect Transistor Device with Blocking Region
#163D semiconductor device and structure with metal layers and memory cells
#173D SEMICONDUCTOR DEVICE AND STRUCTURE WITH SINGLE-CRYSTAL LAYERS
#18METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK-HARMONIC WRINKLE REDUCTION
#19MODULE ASSEMBLY OF MULTIPLE SEMICONDUCTOR DEVICES WITH INSULATING SUBSTRATES
#20METHOD OF MAKING SOI DEVICE FROM BULK SILICON SUBSTRATE AND SOI DEVICE
#21High Voltage Switching Device
#22COMPOSITE SUBSTRATE, MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR DEVICE
#23CAVITY WITH BOTTOM HAVING DIELECTRIC LAYER PORTION OVER GATE BODY WITHOUT ETCH STOP LAYER AND RELATED METHOD
#24HIGH FREQUENCY HETEROJUNCTION BIPOLAR TRANSISTOR DEVICES
#253D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY CELLS AND MULTIPLE METAL LAYERS
#26SEMICONDUCTOR CHIP
#27RADIO FREQUENCY DEVICE
#28METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#29METHODS FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
#30STRUCTURE OF HIGH-RESISTIVITY SILICON-ON-INSULATOR EMBEDDED WITH CHARGE CAPTURE LAYER AND MANUFACTURE THEREOF
#31THIN FILM TRANSISTOR BASED TEMPERATURE SENSOR
#32SELECTIVE POLYSILICON GROWTH FOR DEEP TRENCH POLYSILICON ISOLATION STRUCTURE
#33REDUCING RC DELAY IN SEMICONDUCTOR DEVICES
#34INTEGRATED CHIP WITH GOOD THERMAL DISSIPATION PERFORMANCE
#35HYBRID INTEGRATED CIRCUIT DIES
#36SEMICONDUCTOR DEVICES INCLUDING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) REGIONS
#37SEMICONDUCTOR ON INSULATOR HAVING A SEMICONDUCTOR LAYER WITH DIFFERENT THICKNESSES
#38STRUCTURES AND METHODS FOR TRENCH ISOLATION
#39INTEGRATED CIRCUIT DEVICES INCLUDING INTERGATE SPACER AND METHODS OF FABRICATION THE SAME
#40IC STRUCTURE FOR CONNECTED CAPACITANCES AND METHOD OF FORMING SAME
#41SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FORMED ON SOI SUBSTRATE
#423D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND MEMORY CELLS
#43SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE AND METHOD FOR FORMING
#44Transient stabilized SOI FETs
#45SENSOR SYSTEM WITH A MICROELECTROMECHANICAL SENSOR ELEMENT AND METHOD FOR PRODUCING A SENSOR SYSTEM
#46CONTAMINANT COLLECTION ON SOI
#47BREAKDOWN VOLTAGE CAPABILITY OF HIGH VOLTAGE DEVICE
#48QUANTUM ELECTRONIC CIRCUIT AND METHOD FOR MANUFACTURING THE SAME
#49CONSTRAINED EPITAXIAL FORMATION USING DIELECTRIC WALLS
#50SEMICONDUCTOR DEVICE AND HIGH FREQUENCY SWITCH
#51Low Leakage Replacement Metal Gate FET
#523D semiconductor devices and structures with metal layers
#53METHOD FOR MAKING RADIO FREQUENCY SILICON-ON-INSULATOR (RFSOI) STRUCTURE INCLUDING A SUPERLATTICE
#54HEAT SINK FOR SOI
#55SILICON-ON-INSULATOR SUBSTRATE INCLUDING TRAP-RICH LAYER AND METHODS FOR MAKING THEREOF
#56SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#57Semiconductor Component Including an Electronic Component Based on Polycrystalline Silicon
#58INTEGRATED CIRCUIT DEVICES
#59Semiconductor device
#60RFSOI SEMICONDUCTOR STRUCTURES INCLUDING A NITROGEN-DOPED CHARGE-TRAPPING LAYER AND METHODS OF MANUFACTURING THE SAME
#61METHOD AND APPARATUS IMPROVING GATE OXIDE RELIABILITY BY CONTROLLING ACCUMULATED CHARGE
#62METASURFACE STRUCTURE AND FABRICATION METHOD THEREOF
#63CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN
#64COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE STRUCTURE
#65STRUCTURE WITH ISOLATED WELL
#66SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A PLASMA NITRIDE LAYER AND METHOD OF MANUFACTURE THEREOF
#67STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
#68SEMICONDUCTOR-ON-INSULATOR (SOI) SEMICONDUCTOR STRUCTURES INCLUDING A HIGH-K DIELECTRIC LAYER AND METHODS OF MANUFACTURING THE SAME
#69FIELD-EFFECT TRANSISTORS WITH INTERLEAVED FINGER CONFIGURATION
#70Radio-frequency switching devices having improved voltage handling capability
#71TRANSISTOR STRUCTURES WITH INTERLEAVED BODY CONTACTS AND GATE CONTACTS
#72DIFFUSION BARRIER LAYER FOR SOURCE AND DRAIN STRUCTURES TO INCREASE TRANSISTOR PERFORMANCE
#73LATERAL CAPACITORS OF SEMICONDUCTOR DEVICES
#74DEVICE WITH ISOLATION STRUCTURES IN ACTIVE REGIONS
#75SEMICONDUCTOR PACKAGE STRUCTURE
#763D SEMICONDUCTOR DEVICES AND STRUCTURES WITH METAL LAYERS
#77CRYSTAL GROWING METHOD, APPARATUS AND RF-SOI SUBSTRATE
#78Method for producing 3D semiconductor devices and structures with transistors and memory cells
#793D semiconductor device and structure with bonding and DRAM memory cells
#80MICROELECTRONIC DEVICE WITH IMPROVED VERTICAL BREAKDOWN VOLTAGE
#81Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#82STRUCTURE WITH BACK-GATE HAVING OPPOSITELY DOPED SEMICONDUCTOR REGIONS
#83Semiconductor wafer with devices having different top layer thicknesses
#84METHOD FOR FABRICATING A PATTERNED FD-SOI WAFER
#853D semiconductor memory device and structure with memory and metal layers
#86INTEGRATED STRUCTURE WITH TRAP RICH REGIONS AND LOW RESISTIVITY REGIONS
#87MOSFET TRANSISTOR
#88RF switch device with a sidewall spacer having a low dielectric constant
#89Forksheet transistors with dielectric or conductive spine
#90SEMICONDUCTOR STRUCTURES INCLUDING CONDUCTING STRUCTURE AND METHODS FOR MAKING THE SAME
#91MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application
#92Resistance measuring structures of stacked devices
#93MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES
#94Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#95METHODS AND DEVICES RELATED TO RADIO FREQUENCY DEVICES
#96SEMICONDUCTOR PACKAGE STRUCTURE
#97TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION
#98Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
#99DEVICE WITH LATERALLY GRADED CHANNEL REGION
#100SILICON ON INSULATOR DEVICE
#1013D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY
#1023D semiconductor devices and structures with metal layers
#103Butted body contact for SOI transistor and amplifier circuit
#104COMPLEMENTARY TRANSISTOR AND SEMICONDUCTOR DEVICE
#105FORKSHEET TRANSISTOR STRUCTURES WITH GATE CUT SPINE
#1063D semiconductor device and structure with single-crystal layers
#107Epitaxy Everywhere Based Self-Aligned Direct Backside Contact
#108SEMICONDUCTOR DEVICE
#109TRANSISTORS DESIGNED WITH REDUCED LEAKAGE
#110SET OF INTEGRATED STANDARD CELLS
#111SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#112SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
#1133D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY
#114MOS TRANSISTOR ON SOI STRUCTURE
#115SEMICONDUCTOR DEVICE AND FABRICATING THE SAME
#116SELF-ALIGNED BACKSIDE CONTACT MODULE FOR 3DIC APPLICATION
#117SEMICONDUCTOR DEVICE STRUCTURES ISOLATED BY POROUS SEMICONDUCTOR MATERIAL
#118S-contact for SOI
#119Semiconductor arrangement and method for making
#120NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREFOR
#121Method for Forming SiGe Channel
#122Devices including stacked nanosheet transistors
#123FDSOI DEVICE INCLUDING SELF-ALIGNED DIFFUSION BREAK
#124LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS USING NON-VOLATILE MEMORY CELLS
#125Dynamic body biasing for radio frequency (RF) switch
#126AC Coupling Modules for Bias Ladders
#127SUPPORT SUBSTRATE FOR PASSIVE ELECTRONIC COMPONENT, PASSIVE ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, MATCHING CIRCUIT, AND FILTER CIRCUIT
#128BARIUM TITANATE FILMS HAVING REDUCED INTERFACIAL STRAIN
#129STRUCTURE INCLUDING TRANSISTOR USING BURIED INSULATOR LAYER AS GATE DIELECTRIC AND TRENCH ISOLATIONS IN SOURCE AND DRAIN
#1303D semiconductor device and structure with bonding
#131MICROELECTRONIC DEVICE WITH TWO FIELD-EFFECT TRANSISTORS HAVING A COMMON ELECTRODE
#132DOUBLE SIDE TRANSISTORS ON SAME SILICON WAFER
#133Main-auxiliary field-effect transistor configurations
#134MICROELECTRONIC DEVICE WITH TWO FIELD-EFFECT TRANSISTORS
#135Self-aligned buried power rail cap for semiconductor devices
#136Semiconductor chip
#137SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#138SOI WAFERS AND DEVICES WITH BURIED STRESSORS
#139Stacked semiconductor transistor device with different conductivities having nanowire channels
#140MEMORY DEVICES
#141INTEGRATED CIRCUIT STRUCTURES HAVING AOI GATES WITH ROUTING ACROSS NANOWIRES
#142Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#143SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF
#144SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
#145METHOD AND STRUCTURE OF FORMING SIDEWALL CONTACT FOR STACKED FET
#146Heat pipe for vertically stacked field effect transistors
#147MONOLITHIC MULTI-FETS
#148BIOLOGICAL SENSING SYSTEM HAVING MICRO-ELECTRODE ARRAY
#1493D semiconductor devices and structures with transistors
#150Field effect transistors with reduced leakage current
#151SEMICONDUCTOR DEVICE
#1523D semiconductor device and structure with metal layers
#153METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING BURIED BIAS PAD
#154VTFET WITH BURIED POWER RAILS
#155SEMICONDUCTOR DEVICE
#156INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS
#157SEMICONDUCTOR DEVICE OF THE SILICON ON INSULATOR TYPE AND CORRESPONDING MANUFACTURING METHOD
#158Semiconductor device having a thermal contact and method of making
#159Semiconductor structure and method for manufacturing the same
#1603D semiconductor device and structure with bonding
#161On-Chip Heater
#162An Array Of Capacitors, An Array Of Memory Cells, Method Used In Forming An Array Of Memory Cells, Methods Used In Forming An Array Of Capacitors, And Methods Used In Forming A Plurality Of Horizontally-Spaced Conductive Lines
#163FIELD EFFECT TRANSISTOR WITH SHALLOW TRENCH ISOLATION FEATURES WITHIN SOURCE/DRAIN REGIONS
#164Reducing RC delay in semiconductor devices
#165SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#166NOISE REDUCTION IN SILICON-ON-INSULATOR DEVICES
#167MONOLITHIC INTEGRATION OF DIVERSE DEVICE TYPES WITH SHARED ELECTRICAL ISOLATION
#168INTEGRATED CHIP HAVING A BURIED POWER RAIL
#169SOI Structures with Carbon in Body Regions for Improved RF-SOI Switches
#170GATE STACK DIPOLE COMPENSATION FOR THRESHOLD VOLTAGE DEFINITION IN TRANSISTORS
#171STRUCTURE AND METHOD OF FORMING SPACERS ON UNFACETED RAISED SOURCE/DRAIN REGIONS
#1723D SEMICONDUCTOR DEVICES AND STRUCTURES WITH AT LEAST TWO SINGLE-CRYSTAL LAYERS
#1733D semiconductor device and structure with single-crystal layers
#174Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
#175MULTILAYER ISOLATION STRUCTURE FOR HIGH VOLTAGE SILICON-ON-INSULATOR DEVICE
#176Electrostatic discharge (ESD) protection circuits using tunneling field effect transistor (TFET) and impact ionization MOSFET (IMOS) devices
#177Method to form a fin structure on deep trenches for a semiconductor device
#178CARRIER SUBSTRATE FOR SOI STRUCTURE AND ASSOCIATED MANUFACTURING METHOD
#179Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#180Carbon implantation for thicker gate silicide
#181Semiconductor-on-insulator (SOI) substrate and method for forming
#182HIGH DOSE IMPLANTATION FOR ULTRATHIN SEMICONDUCTOR-ON-INSULATOR SUBSTRATES
#183Method for forming integrated circuit
#184MOS TRANSISTOR ON SOI STRUCTURE
#185Methods and Apparatuses for Use in Tuning Reactance in a Circuit Device
#186Body tie optimization for stacked transistor amplifier
#187Deep nwell contact structures
#188Method of manufacturing semiconductor device
#189DIFFERENT DIFFUSION BREAK STRUCTURES FOR THREE-DIMENSIONAL STACKED SEMICONDUCTOR DEVICE
#190Semiconductor device including high electron mobility transistors with an improved backside electrode being applied in a half-bridge circuit
#191Hybrid Integrated Circuit Dies and Methods of Forming the Same
#192SEMICONDUCTOR-ON-INSULATOR WAFER HAVING A COMPOSITE INSULATOR LAYER
#193Method For Growing Multiple Layers of Source Drain Epitaxial Silicon in FDSOI Process
#194SEMICONDUCTOR DEVICE HAVING A TWO-DIMENSIONAL CHANNEL AND METHOD FOR FABRICATING THE SAME
#195Semiconductor-on-insulator (SOI) semiconductor structures including a high-k dielectric layer and methods of manufacturing the same
#196ADVANCED 3D DEVICE ARCHITECTURE USING NANOSHEETS WITH 2D MATERIALS FOR SPEED ENHANCEMENT
#197Manufacturing method of semiconductor device including field-effect transistor comprising buried oxide (BOX) film and silicon layer
#198Multilevel semiconductor device and structure with oxide bonding
#199Contaminant collection on SOI
#200METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
#201SEMICONDUCTOR DEVICE AND POWER CONVERTER
#202SILICON-ON-INSULATOR SUBSTRATE PROCESSING FOR TRANSISTOR ENHANCEMENT
#203SEMICONDUCTOR-ON-INSULATOR SUBSTRATE FOR RF APPLICATIONS
#204Semiconductor structure and manufacturing method thereof
#205Radio frequency silicon on insulator structure with superior performance, stability, and manufacturability
#206Silicon on insulator semiconductor device with mixed doped regions
#2073D SINGLE CRYSTAL SILICON TRANSISTOR DESIGN INTEGRATED WITH 3D WAFER TRANSFER TECHNOLOGY AND METAL FIRST APPROACH
#208CONNECTIONS FROM BURIED INTERCONNECTS TO DEVICE TERMINALS IN MULTIPLE STACKED DEVICES STRUCTURES
#209TRANSISTOR STACKING BY WAFER BONDING
#210SEMICONDUCTOR DEVICE
#211Bulk Nanosheet with Dielectric Isolation
#212Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drain
#213GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CONTACT SELF-ALIGNED TO EPITAXIAL SOURCE
#2143D semiconductor devices and structures
#215Structure including resistor network for back biasing FET stack
#216Semiconductor structure with a second isolation dam and manufacturing method thereof
#217Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#218METHOD FOR MANUFACTURING A SeOI INTEGRATED CIRCUIT CHIP
#2193D semiconductor device and structure with bonding
#2203D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATES
#221Electronic circuit
#222Semiconductor structure
#223Varactor integrated with complementary metal-oxide semiconductor devices
#224Stacked field-effect transistors with a shielded output
#225METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE
#226Capacitor with an electrode well
#227Gate stack dipole compensation for threshold voltage definition in transistors
#2283D semiconductor device and structure with single-crystal layers
#229EARLY BACKSIDE FIRST POWER DELIVERY NETWORK
#230Body-Source-Tied Transistor
#231Stacked nanosheet gate-all-around device structures
#232DEVICE COMPRISING SPACERS INCLUDING A LOCALISED AIRGAP AND ASSOCIATED MANUFACTURING METHODS
#233Semiconductor structure with shared well
#234Semiconductor memory device, method of manufacturing the same, and electronic device including the same
#235IC structure including porous semiconductor layer under trench isolation
#2363D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REDUNDANCY
#237Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices
#238SOI active transfer board for three-dimensional packaging and preparation method thereof
#239Cross field effect transistor (XFET) library architecture power routing
#240Cross field effect transistor library cell architecture design
#241MULTI-FINGER RF nFET HAVING BURIED STRESSOR LAYER AND ISOLATION TRENCHES BETWEEN GATES
#242Backside electrical contacts to buried power rails
#243Symmetric dual-sided MOS IC
#244RADIO-FREQUENCY INTEGRATED CIRCUITS (RFICS) INCLUDING A POROSIFIED SEMICONDUCTOR ISOLATION REGION TO REDUCE NOISE INTERFERENCE AND RELATED FABRICATION METHODS
#245Semiconductor structures with power rail disposed under active gate
#246Dual strained semiconductor substrate and patterning
#247VTFET with buried power rails
#248Switches with main-auxiliary field-effect transistor configurations
#249CMOS COMPATIBLE BIOFET
#250Self-aligned buried power rail cap for semiconductor devices
#251SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A BURIED HIGH RESISTIVITY LAYER
#252Thermal extraction of single layer transfer integrated circuits
#253Stacked complementary field effect transistors
#254S-contact for SOI
#255Semiconductor device, method of manufacture by monitoring relative humidity, and system of manufacture thereof
#256Bulk substrates with a self-aligned buried polycrystalline layer
#257Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
#258Thin film transistor based temperature sensor
#259Monolithic integration of diverse device types with shared electrical isolation
#260Lateral bipolar transistor structure with marker layer for emitter and collector
#261Method to produce 3D semiconductor devices and structures with memory
#262Nanosheet IC device with single diffusion break
#263Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor
#264Semiconductor memory having both volatile and non-volatile functionality and method of operating
#265RF SWITCH DEVICE AND METHOD OF MANUFACTURING SAME
#266RF SWITCH DEVICE AND METHOD OF MANUFACTURING SAME
#267Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor
#268AC coupling modules for bias ladders
#269STRAINED NANOSHEETS ON SILICON-ON-INSULATOR SUBSTRATE
#270METHODS AND APPARATUSES INVOLVING DIAMOND GROWTH ON GAN
#271Integrated circuit with continuous active region and raised source/drain region
#272Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
#2733D semiconductor memory device and structure
#274Barium titanate films having reduced interfacial strain
#275Semiconductor on insulator having a semiconductor layer with different thicknesses
#276Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
#277Breakdown voltage capability of high voltage device
#278Integrated chip with good thermal dissipation performance
#279BODY CONTACT FET
#280Semiconductor device
#281METHOD FOR FORMING A HANDLING SUBSTRATE FOR A COMPOSITE STRUCTURE INTENDED FOR RF APPLICATIONS AND HANDLING SUBSTRATE
#282MANUFACTURE OF SEMICONDUCTOR DEVICE WITH OPTICAL TRANSMISSION CHANNEL BETWEEN OPTICAL COUPLER AND OUTSIDE OF THE SEMICONDUCTOR DEVICE
#283SUBSTRATE-LESS NANOWIRE-BASED LATERAL DIODE INTEGRATED CIRCUIT STRUCTURES
#284TRANSFER PRINTING FOR RF APPLICATIONS
#285Semiconductor structure and manufacturing method thereof
#286Floating body memory cell having gates favoring different conductivity type regions
#287Semiconductor device and method of fabricating the same
#288MEMS DEVICE COMPRISING AN INSULATED SUSPENDED DIAPHRAGM, IN PARTICULAR PRESSURE SENSOR, AND MANUFACTURING PROCESS THEREOF
#289SEMICONDUCTOR DEVICE
#290Semiconductor memory device
#291INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES WITH DIELECTRIC SPACER FILL
#292Field effect transistor with shallow trench isolation features within source/drain regions
#293Method of making a semiconductor device having a thermal contact
#294Wafer scale bonded active photonics interposer
#295Lateral bipolar junction transistor and method
#2963D semiconductor device and structure with memory
#297SEMICONDUCTOR ELEMENT-USING MEMORY DEVICE
#298SEMICONDUCTOR-ELEMENT-INCLUDING MEMORY DEVICE
#299Semiconductor-element-including memory device
#300Memory device using semiconductor elements