221812 ⎘
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits Multistate logic
BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
#2AUDIO INTERFACE PHYSICAL LAYER
#3BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
#4Scan Flip Flop
#5Audio interface physical layer
#6Bi-directional scan flip-flop circuit and method
#7Logic based ring oscillator coupling circuit
#8PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
#9High to low level shifter architecture using lower voltage devices
#10Flip-flop, master-slave flip-flop, and operating method thereof
#11Protection against side-channel attacks by balancing cell drive polarity
#12Adaptive multibit bus for energy optimization
#13Multi-level output driver with adjustable pre-distortion capability
#14Photonic transmitter drivers with logic using cascaded differential transistor pairs stepped by supply voltage differences
#15Processing-in-memory (PIM) system and operating methods of the PIM system
#16Flip-flop, master-slave flip-flop, and operating method thereof
#17Multi-level spin logic
#18VECTORED FLIP-FLOP
#19Signal isolator with three state data transmission
#20Even/odd die aware signal distribution in stacked die device
#21Multi-level output driver with adjustable pre-distortion capability
#22Information processing device
#23Multiple-state electrostatically-formed nanowire transistors
#24Adaptive multibit bus for energy optimization
#25Vectored flip-flop
#26Standard cell for removing routing interference between adjacent pins and device including the same
#27Wide supply range digital level shifter cell
#28Control of switches in a variable impedance element
#29Read-out techniques for multi-bit cells
#30Multi-level spin logic
#31Detection control device
#32Ultra-Low Power Static State Flip Flop
#33Optimized testing of quantum-logic circuits
#34Pulse-width modulation controller and tri-state voltage generation method
#35Information processing apparatus and semiconductor integrated circuit device
#36Adaptive multibit bus for energy optimization
#37Gate control for a tristate output buffer
#38Integrated circuits with complementary non-volatile resistive memory elements
#39Variable coding method for realizing chip reuse and communication terminal therefor
#40Ultra-low power static state flip flop
#41Buffer stage device that can be connected to a serial peripheral interface bus
#42Control of switches in a variable impedance element
#43Using linked-lists to create feature rich finite-state machines in integrated circuits
#44Self-repairing digital device with real-time circuit switching inspired by attractor-conversion characteristics of a cancer cell
#45Reducing complexity when testing quantum-logic circuits
#46Adaptive multibit bus for energy optimization
#47Time borrowing flip-flop with clock gating scan multiplexer
#48Diagnostic system for a DC-DC voltage converter
#49Clock switch device and system-on-chip having the same
#50Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit
#51Method for managing the operation of a low-complexity synchronous retention flip-flop circuit, and corresponding circuit
#52Multi-level output driver with adjustable pre-distortion capability
#53Time borrowing flip-flop with clock gating scan multiplexer
#54Using direct sums and invariance groups to test partially symmetric quantum-logic circuits
#55Vectored flip-flop
#56Register circuit
#57Standard cell for removing routing interference between adjacent pins and device including the same
#58Tri-state inverter, D latch and master-slave flip-flop comprising TFETs
#59METHOD AND APPARATUS FOR SIMULTANEOUS PROCESSING OF MULTIPLE FUNCTIONS
#60Multiple state electrostatically formed nanowire transistors
#61Low-power, small-area, high-speed master-slave flip-flop circuits and devices including same
#62Dual voltage supply
#63Three state latch
#64Ultra-low power static state flip flop
#65Semiconductor integrated circuit and high frequency antenna switch
#66Data processing device, data processing method, and computer program
#67Method and apparatus for simultaneous processing of multiple functions
#68RECEIVING AN I/O SIGNAL IN MULTIPLE VOLTAGE DOMAINS
#69Receiving an I/O signal in multiple voltage domains
#70Circuit for low-power ternary domino reversible counting unit
#71Semiconductor device
#72Multi-level signaling
#73Non-volatile boolean logic operation circuit and operation method thereof
#74Dual-rail encoding
#75Radiation hardened by design digital input/output circuits and related methods
#76Four-state input detection circuitry
#77Integrated device with auto configuration
#78Pulse synthesizing circuit
#79Three state latch
#80Bidirectional data exchange circuit
#81Multi-value logic signaling in multi-functional circuits
#82Multi-level signaling
#83Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit
#84Pre-emphasis control circuit for adjusting the magnitude of a signal over a period according to a fraction of a bit-time
#85Method and apparatus for simultaneous processing of multiple functions
#86Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit
#87SEMICONDUCTOR DEVICE INCLUDING A TEST CIRCUIT OF A MULTIVALUED LOGIC CIRCUIT HAVING AN IMPEDANCE CONTROL
#88Four logic state voltage to two output decompressor IC
#89Low power multi-level signaling
#90Multi-level transmitter circuit having substantially constant impedance output
#91Multi-value logic signaling in multi-functional circuits
#92QUAD STATE LOGIC DESIGN METHODS, CIRCUITS AND SYSTEMS
#93Multivalued logic circuit
#94Apparatus and method to tolerate floating input pin for input buffer
#95Multi-level signaling
#96Quad to binary converter with directly connected and coupled outputs
#97Data transmitter and related semiconductor device
#98Semiconductor device including a test circuit of a multivalued logic circuit having an impedance control
#99Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit
#100Multivalued logic circuit
#101Multi-state latches from n-state reversible inverters
#102Multi-level signaling
#103Ternary valve input circuit
#104METHOD AND APPARATUS FOR SIMULTANEOUS PROCESSING OF MULTIPLE FUNCTIONS
#105Three-valued logic function circuit
#106Multi-level signaling for low power, short channel applications
#107Quad state to two state interface circuitry with clock input
#108Clock regeneration circuit
#109Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry
#110Semiconductor integrated circuit and method of controlling the same
#111Multi-state latches from n-state reversible inverters
#112Binary boolean output on input with more than two states
#113Variable Threshold Transistor For The Schottky FPGA And Multilevel Storage Cell Flash Arrays
#114VARIABLE THRESHOLD TRANSISTOR FOR THE SCHOTTKY FPGA AND MULTILEVEL STORAGE CELL FLASH ARRAYS
#115Single and composite binary and multi-valued logic functions from gates and inverters
#116Ternary pulse generation circuit
#117Operations with logical states from a four voltage level signal
#118SCL type FPGA with multi-threshold transistors and method for forming same
#119Variable threshold transistor for the Schottky FPGA and multilevel storage cell flash arrays
#120Quaternary and trinary logic switching circuits
#121SCL type FPGA with multi-threshold transistors and method for forming same
#122Single and composite binary and multi-valued logic functions from gates and inverters
#123Quad state memory with converter feedback, transmission, and clock circuitry
#124Delay lock loop circuit
#125Signal arbiter
#126Even/odd die aware signal distribution in stacked die device
#127Dynamic decode circuit low power application
#128Dynamic decode circuit low power application
#129Bistable-element for random number generation
#130Bistable-element for random number generation
#131Tristate multiplexers with immunity to aging effects
#132Integrated clock gating cell using a low area and a low power latch