221811 ⎘
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits
Sub-classes:SEMICONDUCTOR METAL LAYER STRUCTURE OVER CELL REGION
#2DIGITAL SWITCHING ACTIVITY SENSING
#3SWITCH CIRCUIT
#4HIGH SPEED RIPPLE ADDER
#5ORTHOGONAL PROTEIN HETERODIMERS
#6Method for supporting multiple concurrent plugins in a programmable integrated circuit
#7DIGITAL SWITCHING ACTIVITY SENSING
#8SEMICONDUCTOR METAL LAYER STRUCTURE OVER CELL REGION
#9Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device
#10RAPID TEMPERATURE CHANGE DETECTION USING SLEW RATE
#11Integrated circuit device with embedded programmable logic
#12Engineering change order cell structure having always-on transistor
#13Orthogonal protein heterodimers
#14QUANTUM CIRCUIT AND METHODS FOR USE THEREWITH
#15Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method
#16Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method
#17High-voltage voltage level converter
#18ANALYSIS METHOD AND ANALYSIS SYSTEM
#19Integrated circuit device with embedded programmable logic
#20Engineering change order cell structure having always-on transistor
#21False path timing exception handler circuit
#22Semiconductor device and memory system
#23Systems and methods for hybrid analog and digital processing of a computational problem using mean fields
#24Systems and methods for calibrating impedance of a low power voltage-mode transmitter driver
#25Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device
#26Multi-bit standard cell
#27Transmitter circuitry with N-type pull-up transistor and low output voltage swing
#28Computer product for making a semiconductor device
#29Engineering change order cell structure having always-on transistor
#30Semiconductor device and memory system
#31Synapse circuit and arithmetic device
#32Integrated circuit device with embedded programmable logic
#33False path timing exception handler circuit
#34Digital design with bundled data asynchronous logic and body-biasing tuning
#35Systems and methods to switch radio frequency signals for greater isolation
#36Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device
#37Semiconductor integrated circuit
#38Data storage for accelerating functions
#39Discrete input
#40Systems and methods to switch radio frequency signals for greater isolation
#41False path timing exception handler circuit
#42CLOCK MANAGEMENT BLOCK
#43Semiconductor integrated circuit
#44Impedance matching circuits and interface circuits
#45Integrated circuit devices
#46Power gating circuit utilizing double-gate fully depleted silicon-on-insulator transistor
#47Integrated circuit design using generation and instantiation of circuit stencils
#48Reuse of extracted layout-dependent effects for circuit design using circuit stencils
#49Power control circuitry for controlling power domains
#50REFERENCE VOLTAGE BUFFER CIRCUIT
#51Reuse of extracted layout-dependent effects for circuit design using circuit stencils
#52Switching circuit for radio frequency isolation in a portable transceiver
#53Integrated circuit device with embedded programmable logic
#54Network logic synthesis
#55Techniques for forming a compacted array of functional cells
#56Signal multiplexer
#57Multi-wire open-drain link with data symbol transition based clocking
#58Semiconductor device
#59Reconfigurable semiconductor integrated circuit and electronic device
#60Systems and methods to switch radio frequency signals for greater isolation
#61Logic circuit and system and computer program product for logic synthesis
#62Integrated clock gater (ICG) using clock cascode complimentary switch logic
#63Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same
#64Clock management block
#65Differential signal reversion and correction circuit and method thereof
#66Integrated clock gater (ICG) using clock cascode complimentary switch logic
#67Semiconductor apparatus
#68Slew rate control for multiple voltage domains
#69Embedded resilient buffer
#70Switching circuit and semiconductor memory device
#71Output circuit
#72Semiconductor device and semiconductor system including the same
#73Multi-wire open-drain link with data symbol transition based clocking
#74Methods, integrated circuits, apparatuses and buffers with adjustable drive strength
#75Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
#76Output driver for energy recovery from inductor based sensor
#77Configurable single-ended driver
#78Bypassable clocked storage circuitry for dynamic voltage-frequency scaling
#79Zero keeper circuit with full design-for-test coverage
#80Receiving circuits for core circuits
#81Voltage-aware signal path synchronization
#82Start-up circuit for an output driver
#83Output driver using low voltage transistors
#84Method for driving semiconductor device
#85Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits
#86Semiconductor device
#87Source series terminated driver circuit with programmable output resistance, amplitude reduction, and equalization
#88Arbiter for asynchronous state machines
#89Optical proximity correction for active region design layout
#90Self-disabling chip enable input
#91Receiver circuit
#92Semiconductor device and method of manufacturing the same
#93Apparatuses, integrated circuits, and methods for testmode security systems
#94Critical-path circuit for performance monitoring
#95ERROR DETECTION CODE ENHANCED SELF-TIMED/ASYNCHRONOUS NANOELECTRONIC CIRCUITS
#96SYSTEM AND METHOD OF TEST MODE GATE OPERATION
#97Synchronizing timing of communication between integrated circuits
#98Optical proximity correction for active region design layout
#99Methods, integrated circuits, apparatuses and buffers with adjustable drive strength
#100One-of-n N-nary logic implementation of a storage cell
#101Digital Output Driver
#102Self-disabling chip enable input
#103Stage circuit and scan driver using the same
#104High performance pre-mixer buffer in wireless communications systems
#105Receiving circuits for core circuits
#106Reference voltage stabilization apparatus and method
#107Reduced swing signal
#108Memristor apparatus
#109Differential signal termination circuit
#110Critical-path circuit for performance monitoring
#111Configuration method and FPGA circuit re-executing configuration based on adjusted configuration data
#112System and method of test mode gate operation
#113Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits
#114Data holding circuit
#115Apparatus and method for generating resistance calibration code in semiconductor integrated circuit
#116Logic modules for semiconductor integrated circuits
#117Apparatus and method for generating a constant logical value in an integrated circuit
#118Method for managing proposals in a distributed computing system
#119Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits
#120Circuit arrangement and method for processing a dual-rail signal
#121Distributed computing systems and system components thereof
#122Integrated circuits including auxiliary resources
#123System and method for synthetic antiferromagnet skyrmion based logic device
#124Circuit architecture for expanded design for testability functionality
#125Integrated circuit device with embedded programmable logic
#126Timing path slack monitoring system
#127Memory blocks with shared address bus circuitry
#128Method and apparatus for preventing accelerated aging of a physically unclonable function