TRIPLE MODULE REDUNDANT SOLID STATE POWER SWITCH

RADIATION HARDENED LOW NOISE POWER MANAGEMENT DEVICE

SINGLE EVENT UPSET HARDENED FLIP-FLOP AND METHODS OF OPERATION

FLIP-FLOP WITH SELF CORRECTION

Semiconductor device

Circuit for mitigating single-event-transients

Fault resilient flip-flop with balanced topology and negative feedback

Triple modular redundancy flip-flop with improved power performance area and design for testability

Circuit arrangements and methods for forming the same

Circuit, method for sizing an aspect ratio of transistors of a circuit, and circuit arrangement

SEMICONDUCTOR INTEGRATED CIRCUIT WITH RADIATION RESISTANCE

Flip-flop with soft error tolerance

Circuit and method of forming the same

Soft error-resilient latch

Single event latchup recovery with state protection

Compensating for degradation of electronics due to radiation vulnerable components

Radiation-resistant asynchronous communications

Radiation-damage-compensation-circuit and SOI-MOSFET

Level shifter circuit, corresponding device and method

Digital register component and analog-digital converter detecting signal distortion in high-radiation environments

Dual interlocked logic circuits

High voltage tolerant CMOS driver for low-voltage bi-directional communication buses

Tristate and cross current free output buffer

HARDENED STORAGE ELEMENT

Data register for radiation hard applications

Semiconductor device

Radiation hardened by design digital input/output circuits and related methods

Communication apparatus with slew rate feedback

Integrated circuit having improved radiation immunity

Soft error and radiation hardened sequential logic cell

Single event transient and upset mitigation for silicon-on-insulator CMOS technology

Soft error resilient circuit design method and logic cells

Radiation-tolerant overcurrent detection

LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL

Integrated circuit elementary cell with a low sensitivity to external disturbances

(N-1)-out-of-N voter mux with enhanced drive

Electronic circuit arrangement for processing binary input values

Layout method for soft-error hard electronics, and radiation hardened logic cell

Radiation hardened circuit design for multinode upsets

Semiconductor integrated circuit device

Logic circuit protected against transient disturbances

Soft error hard electronic circuit and layout

Fault tolerant asynchronous circuits

SEU tolerant arbiter

Low voltage, high speed data latch

Fault triggerred automatic redundancy scrubber

Semiconductor integrated circuit having latch circuit applied changeable capacitance and method thereof

Method and apparatus for an event tolerant storage circuit

Logic circuit protected against transient disturbances

ELECTRONIC DEVICE HAVING LOGIC CIRCUITRY AND METHOD FOR DESIGNING LOGIC CIRCUITRY

LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL

SEU hardening circuit and method

Set dominant latch with soft error resiliency

Method for radiation tolerance by logic book folding

Fault tolerant asynchronous circuits

APPARATUS AND METHOD OF ERROR DETECTION AND CORRECTION IN A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY FIELD-PROGRAMMABLE GATE ARRAY

Integrated circuit

RADIATION TOLERANT ELECTROSTATIC DISCHARGE PROTECTION NETWORKS

SET HARDENED REGISTER

LOCAL CONTROLLER FOR RECONFIGURABLE PROCESSING ELEMENTS

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Semiconductor integrated circuit device

Fault tolerant asynchronous circuits

Logic circuit protected against transitory perturbations

Radiation hardened differential output buffer

Circuit for distributing an initial signal with a tree structure, protected against logic random events

Radiation hardened logic circuit

Semiconductor integrated circuit

Radiation tolerant combinational logic cell

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Dual redundant dynamic logic

Dual path redundancy with stacked transistor voting

Radiation tolerant electrostatic discharge protection networks

Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit

Logic cell with two isolated redundant outputs, and corresponding integrated circuit

Redundancy circuits hardened against single event upsets

Method and system for reducing glitch effects within combinational logic

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Pulse-rejecting circuit for suppressing single-event transients

Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions

Method and apparatus for providing SEU-tolerant circuits

Radiation-tolerant inrush limiter

Radiation tolerant DC/DC converter with non-radiation hardened parts

Single event upset immune keeper circuit and method for dual redundant dynamic logic

Data retaining circuit

Data retaining circuit

Data retaining circuit

Radiation hardening of logic circuitry using a cross enabled, interlocked logic system and method

Redundant single event upset supression system

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Radiation hardened housekeeping slave node (RH-HKSN) application specific integrated circuit (ASIC) element

Complementary self-limiting logic

Radiation event protection circuit with double redundancy and latch

Circuit for and method of storing data in an integrated circuit device

Radiation-hardened CMOS logic device

Charge steering latch for low soft error rate

Radiation hardened structured ASIC platform with compensation of delay for temperature and voltage variations for multiple redundant temporal voting latch technology