221959 ⎘
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form; Structural details of configuration resources for reliability
Method and System for Redundancy Switch Between Two Controllers for Supplementary Damping of Governor
#2MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
#33D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
#4RECONFIGURABLE PUF WITH TWO PUF FUNCTIONS
#53D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
#6COMPUTATIONAL UNIT OF A CONFIGURABLE INTEGRATED UNIT INTENDED TO IMPROVE THE MANAGEMENT OF A DATA FLOW
#7Programmable stream switches and functional safety circuits in integrated circuits
#8Clock Insertion Delay Systems and Methods
#9MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
#10Multiple partitions in a data processing array
#11Hybrid synchronous and asynchronous control for scan-based testing
#12Signal generation circuit, micro-controller, and control method thereof
#13Reference buffer
#14Multi-die FPGA implementing built-in analog circuit using active silicon connection layer
#15Semiconductor device and memory system
#16Techniques for reducing uneven aging in integrated circuits
#17TIME OF FLIGHT SENSING UNIT HAVING RECONFIGURABLE OR LOGIC
#183D stacked integrated circuits having failure management
#19Input/output bus protection systems and methods for programmable logic devices
#20Embedded logic analyzer and integrated circuit including the same
#21Semiconductor device and memory system
#223D SEMICONDUCTOR DEVICE AND STRUCTURE
#233D SEMICONDUCTOR DEVICE AND STRUCTURE
#24FLEXIBLE LOGIC UNIT ADAPTED FOR REAL-TIME TASK SWITCHING
#25Method for programming a field programmable gate array and network configuration
#263D stacked integrated circuits having failure management
#273D stacked integrated circuits having failure management
#28Programmable Circuit Having Multiple Sectors
#29Standard cell for removing routing interference between adjacent pins and device including the same
#30Semiconductor device and memory system
#31Electronic controller and control method thereof, and electronic control system
#32Non-volatile multiple time programmable integrated circuit system with selective conversion to one time programmable or permanent configuration bit programming capabilities and related methods
#33Method and apparatus of using parity to detect random faults in memory mapped configuration registers
#34System and method for testing and configuration of an FPGA
#35Power control for a dataflow processor
#36METHODS TO PRODUCE A 3D SEMICONDUCTOR MEMORY DEVICE AND SYSTEM
#37Scalable micro bumps indexing and redundancy scheme for homogeneous configurable integrated circuit dies
#38METHOD FOR PRODUCING A 3D MEMORY DEVICE
#393D SEMICONDUCTOR DEVICE AND SYSTEM
#40Dynamic parameter operation of an FPGA
#41Validating an image for a reconfigurable device
#423D SEMICONDUCTOR DEVICE AND SYSTEM
#43Integrated circuits with in-field diagnostic and repair capabilities
#44Dynamic multicycles for core-periphery timing closure
#45Techniques for reducing uneven aging in integrated circuits
#46Systems and methods for dynamic voltage and frequency scaling in programmable logic devices
#47Logical elements with switchable connections in a reconfigurable fabric
#483D SEMICONDUCTOR DEVICE AND SYSTEM
#493D SEMICONDUCTOR DEVICE AND SYSTEM
#503D SEMICONDUCTOR DEVICE AND SYSTEM
#51Methods for handling integrated circuit dies with defects
#52A 3D SEMICONDUCTOR DEVICE AND SYSTEM
#533D SEMICONDUCTOR DEVICE AND SYSTEM
#54Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
#55Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
#56Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features
#573D SEMICONDUCTOR DEVICE AND SYSTEM
#583D SEMICONDUCTOR DEVICE AND SYSTEM
#593D SEMICONDUCTOR DEVICE AND SYSTEM
#603D SEMICONDUCTOR DEVICE AND SYSTEM
#61Time of flight sensing unit having reconfigurable OR logic
#62Digital integrated circuit protected from transient errors
#633D semiconductor device and system
#64Circuit configuration optimization apparatus and machine learning device for learning a configuration of a field programmable gate array (FPGA) device
#65Field programmable logic array
#66System and method for testing and configuration of an FPGA
#67System, apparatus and method for multi-kernel performance monitoring in a field programmable gate array
#68A Reconfigurable Hardware Device for Providing a Reliable Output Signal as well as a Method for Providing Said Reliable Output
#693D semiconductor device, fabrication method and system
#70Noise-immune reference (NREF) integrated in a programmable logic device
#71Selection of multiple configuration settings using a single configuration terminal
#72Semiconductor device and memory system
#73Noise-immune reference (NREF) integrated in a programmable logic device
#74Power control within a dataflow processor
#75Integrated circuit with spare cells
#76Standard cell for removing routing interference between adjacent pins and device including the same
#77COMMUNICATION APPARATUS, SEMICONDUCTOR DEVICE, AND FREQUENCY CHARACTERISTIC CHANGING METHOD
#78DYNAMIC PARAMETER OPERATION OF AN FPGA
#79Configurable hardware platform for measurement or control
#80Circuit arrangement for a safety IandC system
#81DESIGNING PROGRAM OF PROGRAMMABLE LOGIC DEVICE, PROGRAMMABLE LOGIC DEVICE DESIGNING APPARATUS, AND METHOD THEREOF
#82Integrated circuit having spare circuit cells
#83Semiconductor device, electronic component, and electronic device
#84Integrated circuit verification using parameterized configuration
#85Semiconductor device, electronic component, and electronic device
#86Embedded logic analyzer and integrated circuit including the same
#87Programmable device, error storage system, and electronic system device
#88Programmable logic device and semiconductor device
#89Programmable device, information processing device, and control method for processing circuit of programmable device
#90Programmable logic device and logic integration tool
#91Integrated circuit having spare circuit cells
#92Ladder program retrieval device capable of retrieving ladder circuits based on specified signal operation conditions
#93System and method for managing pipelines in reconfigurable integrated circuit architectures
#94Systems and methods for maintaining memory access coherency in embedded memory blocks
#95Chip and method for identifying a chip
#96Filtering event log entries
#97Programmable circuit having multiple sectors
#98Runtime loading of configuration data in a configurable IC
#99Spare gate cell for integrated circuit
#100Verification and certification of an electronic component
#101Programmable circuit device and configuration information restoration method
#102CIRCUIT AND METHOD OF CONTROLLING A CIRCUIT
#103Diagnosis device, control method of diagnosis device, and recording medium
#104Logical elements with switchable connections
#105Memory element and programmable logic device
#106Optoelectronic safety sensor
#107Reconfiguring an ASIC at runtime
#108Reprogrammable logic device resistant to radiations
#109Self-healing, fault-tolerant FPGA computation and architecture
#110Micro-granular delay testing of configurable ICs
#111Nonvolatile resistor network assembly and nonvolatile logic gate with increased fault tolerance using the same
#112Look-up table
#113Semiconductor integrated circuit, programmable logic device, method of manufacturing semiconductor integrated circuit
#114Filtering event log entries
#115Program Binding System, Method and Software for a Resilient Integrated Circuit Architecture
#116Trigger circuits and event counters for an IC
#117Field programmable gate array utilizing two-terminal non-volatile memory
#118Field programmable gate array utilizing two-terminal non-volatile memory
#119Runtime loading of configuration data in a configurable IC
#120Semiconductor integrated circuit, programmable logic device, method of manufacturing semiconductor integrated citcuit
#121Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
#122Soft error resilient FPGA
#123Delay-insensitive asynchronous circuit
#124Soft error resilient FPGA
#125Integrated circuits with shared interconnect buses
#126Safety component in a programmable components chain
#127Control system, logic module substrate, and logic FPGA
#128Field programmable gate array utilizing two-terminal non-volatile memory
#129Methods and structure for source synchronous circuit in a system synchronous platform
#130Apparatus for improving reliability of electronic circuitry and associated methods
#131Semiconductor device
#132Programmable logic device
#133IC with deskewing circuits
#134State-monitoring memory element
#135Volatile memory elements with soft error upset immunity
#136EMBEDDED BLOCK CONFIGURATION VIA SHIFTING
#137Element controller for a resilient integrated circuit architecture
#138Fault tolerant integrated circuit architecture
#139Micro-granular delay testing of configurable ICs
#140Runtime loading of configuration data in a configurable IC
#141Resilient integrated circuit architecture
#142Skew management in an interconnection system
#143RC delay detectors with high sensitivity for through substrate vias
#144Method for fabrication of a semiconductor device and structure
#145Fault tolerant integrated circuit architecture
#146Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
#147Configuration method and FPGA circuit re-executing configuration based on adjusted configuration data
#148Trigger circuits and event counters for an IC
#149Trigger circuits and event counters for an IC
#150Programmable logic device having an embedded test logic with secure access control
#151Error detection on programmable logic resources
#152IC with deskewing circuits
#153Micro-granular delay testing of configurable ICs
#154Accessing multiple user states concurrently in a configurable IC
#155Skew management in an interconnection system
#156Methods and circuitry for reconfigurable SEU/SET tolerance
#157METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES
#158Fault tolerant integrated circuit architecture
#159Circuits and methods for testing FPGA routing switches
#160Element controller for a resilient integrated circuit architecture
#161Runtime loading of configuration data in a configurable IC
#162Method for fabrication of a semiconductor device and structure
#163Configuration network for an IC
#164Resilient integrated circuit architecture
#165Volatile memory elements with soft error upset immunity
#166Volatile memory elements with soft error upset immunity
#167RANDOM GENERATION OF PLD CONFIGURATIONS TO COMPENSATE FOR DELAY VARIABILITY
#168Programmable logic device having an embedded test logic with secure access control
#169Programmable logic circuit
#170Error detection and location circuitry for configuration random-access memory
#171Configuration data feeding device
#172Power-on-reset circuitry
#173Circuits and methods for testing FPGA routing switches
#174Multi-row block supporting row level redundancy in a PLD
#175Reconfigurable computing device and method for inspecting configuration data
#176Fault tolerant integrated circuit architecture
#177Error detection on programmable logic resources
#178Integrated circuit design method for improved testability
#179RECONFIGURABLE CIRCUIT WITH REDUNDANT RECONFIGURABLE CLUSTER(S)
#180Fault tolerant integrated circuit architecture
#181Resilient integrated circuit architecture
#182FPGA configuration protection and control using hardware watchdog timer
#183Debug network for a configurable IC
#184Skew management in an interconnection system
#185Error-detecting and correcting FPGA architecture
#186Reconfigurable device
#187Transport network for a configurable IC
#188Configurable IC with deskewing circuits
#189Retrieving data from a configurable IC
#190Element controller for a resilient integrated circuit architecture
#191APPARATUS AND METHOD OF ERROR DETECTION AND CORRECTION IN A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY FIELD-PROGRAMMABLE GATE ARRAY
#192Random access of user design states in a configurable IC
#193Runtime loading of configuration data in a configurable IC
#194System comprising a state-monitoring memory element
#195Runtime loading of configuration data in a configurable IC
#196Power-on-reset circuitry
#197Method and device for programming anti-fuses
#198Configuration network for a configurable IC
#199Checkpointing user design states in a configurable IC
#200Programmable logic device having redundancy with logic element granularity
#201Redundant configuration memory systems and methods
#202Configurable IC with packet switch network
#203Accessing multiple user states concurrently in a configurable IC
#204Configurable IC with trace buffer and/or logic analyzer functionality
#205Error detection on programmable logic resources
#206Program binding system, method and software for a resilient integrated circuit architecture
#207Compiler system, method and software for a resilient integrated circuit architecture
#208Element controller for a resilient integrated circuit architecture
#209Resilient integrated circuit architecture
#210Fault tolerant integrated circuit architecture
#211Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
#212Resilient integrated circuit architecture
#213Fault tolerant integrated circuit architecture
#214Soft error location and sensitivity detection for programmable devices
#215Runtime reconfiguration of reconfigurable circuits
#216Dynamic peripheral function remapping to external input-output connections of an integrated circuit device
#217Versatile logic element and logic array block
#218Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets
#219Reconfigurable system and method with corruption detection and recovery
#220Method for increasing the manufacturing yield of programmable logic devices
#221Deterministic addressing of nanoscale devices assembled at sublithographic pitches
#222Runtime reconfiguration of reconfigurable circuits
#223Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
#224Reconfigurable circuit with redundant reconfigurable cluster(s)
#225Self test structure for interconnect and logic element testing in programmable devices
#226Semiconductor integrated circuit device
#227Rapid interconnect and logic testing of FPGA device
#228Customizable and Programmable Cell Array
#229Configuration circuit for programmable logic devices
#230Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
#231Programmable logic device, information processing device and programmable logic device control method
#232Programmable logic device
#233Customizable and programmable cell array
#234FPGA-based digital circuit for reducing readback time
#235Redundancy structures and methods in a programmable logic device
#236Reconfiguration port for dynamic reconfiguration-system monitor interface
#237Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array
#238Versatile logic element and logic array block
#239Continuous self-verify of configuration memory in programmable logic devices
#240Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
#241Programmable broadcast initialization of memory blocks
#242Customizable and programmable cell array
#243Customizable and programmable cell array
#244Array of programmable cells with customized interconnections
#245Circuit for and method of storing data in an integrated circuit device
#246Validating an image for a reconfigurable device
#247Multi-buffered shift register input matrix to FPGA
#248Field programmable gate array utilizing two-terminal non-volatile memory
#249Circuit for and method of enabling the selection of a circuit
#250Techniques for bypassing defects in rows of circuits
#251Mitigation of single event latchup
#252Physically unclonable circuit having a programmable input for improved dark bit mask accuracy
#253Voting circuit and self-correcting latches
#254Power distribution network IP block
#255Partial discharge signal normalization
#256TSV redundancy scheme and architecture using decoder/encoder
#257Configuring a programmable logic device using a configuration bit stream without phantom bits
#258Methods and apparatus for transmitting a signal in a single direction using bidirectional driver circuits
#259Diagnostic coverage of registers by software
#260Programmable IC with power fault tolerance
#261Safety hardware and/or software fault tolerance using redundant channels
#262Single event upset mitigation
#263System and method for searching multiple boot devices for boot images
#264Method and apparatus for providing signal routing control