221979 ⎘
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits; EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
Sub-classes:ANALOG CIRCUIT
#2GATE DRIVER CIRCUIT and CHIP
#3METHOD FOR ALLEVIATING LEAKAGE DEGRADATION EFFECT IN GaN DEVICE
#4LOW-DROPOUT REGULATOR CIRCUIT WITH ADAPTIVE TRANSISTOR WELL SWITCHING
#5SEQUENTIAL CIRCUIT BASED OSCILLATOR
#6POWER STAGE PROVIDING HIGHER MAGNITUDE CURRENT IN A SWITCHING CONVERTER
#7STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS
#8APPARATUS AND METHOD WITH IN-MEMORY COMPUTING (IMC) PROCESSOR
#9Apparatus comprising a comparator circuit
#10Apparatus and method for generating low-density parity-check (LDPC) code
#11Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
#12High-speed communication link with self-aligned scrambling
#13Data multiplexer single phase flip-flop
#14Fabrication of a majority logic gate having non-linear input capacitors
#15Low-loss arithmetic circuit and operating method of the same
#16Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
#17APPARATUS FOR GENERATING RANDOM DATA AND A METHOD THEREOF
#18In-memory computing device supporting arithmetic operations
#19Level shifter circuit with intermediate power domain
#20Three-input exclusive NOR/OR gate using a CMOS circuit
#21Clockless delay adaptation loop for random data
#22Static random-access memory (SRAM) compute in-memory integration
#23Full adder cell with improved power efficiency
#24Full adder cell with improved power efficiency
#25Computational memory cell and processing array device using complementary exclusive or memory cells
#26Data compressor logic circuit
#27Logical operations using a logical operation component
#28Compact 3D stacked-CFET architecture for complex logic cells
#29Three-port memory cell and array for in-memory computing
#30Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
#31Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
#32Data compressor logic circuit
#33In memory computing (IMC) memory circuit having 6T cells
#34Performing logical operations using a logical operation component based on a rate at which a digit line is discharged
#35Logic gate designs for 3D monolithic direct stacked VTFET
#36Method and circuit for de-biasing PUF bits
#37Methods and devices for detecting open and/or shorts circuits in MEMS micro-mirror devices
#38Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
#39Logic gate designs for 3D monolithic direct stacked VTFET
#40Memory device with multiple memory arrays to facilitate in-memory computation
#41SYSTEM AND METHOD FOR TUNABLE PRECISION OF DOT-PRODUCT ENGINE
#42Low power 25% duty cycle local oscillator clock generation circuit
#43Radio frequency switching circuitry with reduced switching time
#44Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing
#45Pulse triggered flip flop
#46Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
#47Code word generating method, erroneous bit determining method, and circuits thereof
#48Logic unit circuit and pixel driving circuit
#49Manufacturability (DFM) cells in extreme ultra violet (EUV) technology
#50DYNAMIC IMPEDANCE CONTROL FOR VOLTAGE MODE DRIVERS
#51Pulse triggered flip flop
#52Logic circuitry using three dimensionally stacked dual-gate thin-film transistors
#53Pulsed semi-dynamic fast flip-flop with scan
#54Linear masking circuits for side-channel immunization of advanced encryption standard hardware
#55Current-controlled CMOS logic family
#56Register circuit
#57Integrated circuit with spare cells
#58Circuitry and layouts for XOR and XNOR logic
#59Ultralow power carbon nanotube logic circuits and method of making same
#60Methods and devices for detecting open and/or shorts circuits in MEMS micro-mirror devices
#61Semiconductor chip using logic circuitry including complementary FETs for reverse engineering protection
#62Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
#63Thyristor-based optical XOR circuit
#64Frequency doubler
#65Threshold logic element with stabilizing feedback
#66Threshold logic gates with resistive networks
#67Current-controlled CMOS logic family
#68Chip and method for manufacturing a chip
#69Circuitry and layouts for XOR and XNOR logic
#70Controllable polarity FET based arithmetic and differential logic
#71Soft error resilient circuit design method and logic cells
#72Logic circuit performing exclusive or operation and data processing system including the same
#73SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
#74Current-controlled CMOS logic family
#75Nonvolatile full adder circuit
#76Semiconductor integrated circuit
#77High-speed static XOR circuit
#78Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics
#79Circuitry and layouts for XOR and XNOR logic
#80Current-controlled CMOS logic family
#81Current-controlled CMOS logic family
#82XOR logic circuit
#83Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby
#84Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby
#85Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit
#86Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics
#87Critical path monitor for an integrated circuit and method of operation thereof
#88Current-controlled CMOS logic family
#89Efficient XOR calculation
#90Combinatorial logic circuit
#91Current-controlled CMOS logic family
#92High speed, low power CMOS logic gate
#93Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices
#94Device for comparing two words of n bits each
#95Monitoring and controlling power consumption in a sequential logic circuit
#96XOR circuit
#97Distributed delay-locked-based clock and data recovery systems
#98Exclusive-or and/or exclusive-nor circuits including output switches and related methods
#99Current-controlled CMOS logic family
#100Logic circuit combining exclusive OR gate and exclusive NOR gate
#101Logic circuit
#102Symmetric and non-stacked XOR circuit
#103One-level zero-current-state exclusive or (XOR) gate
#104Current-controlled CMOS logic family
#105Circuit for controlling the time duration of a signal
#106Power converter circuitry and method
#107Linear full-rate phase detector and clock and data recovery circuit
#108One-level zero-current-state exclusive or (XOR) gate
#109Gray code counter
#110Multibit bit adder
#1114-2 Compressor
#112Distributed delay-locked-based clock and data recovery systems
#113High-speed communication link with self-aligned scrambling
#114Majority logic gate with non-linear input capacitors
#115Processing method for applying analog dynamic circuit to digital testing tool
#116Clockless delay adaptation loop for random data
#117Static random-access memory (SRAM) for in-memory computing
#118Self-gating flip-flop
#119Reprogrammable phononic metasurfaces