ClassID:

221506

H03K2005/00247 - CPC Classification

Classification description:

Manipulating of pulses not covered by one of the other main groups of this subclass; Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse; Layout of the delay element using circuits having two logic levels using counters

Recent Application in this class:
#1
20260135547
2026-05-14

SYSTEMS AND METHODS FOR A TIME DOMAIN VOLTAGE REFERENCE WITH ZERO QUIESCENT CURRENT CONSUMPTION

#2
20260121624
2026-04-30

METHODS AND APPARATUS TO IMPLEMENT DELAY LINES AND ANALOG TO DIGITAL CONVERTERS

#3
20260106607
2026-04-16

SEMICONDUCTOR DEVICE

#4
20260050379
2026-02-19

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

#5
20250309877
2025-10-02

SELF-CALIBRATION OF DELAY CIRCUITS IN ASYNCHRONOUS LOOPS

#6
20240168636
2024-05-23

Clock mode determination in a memory system

#7
20230384935
2023-11-30

Clock mode determination in a memory system

#8
20230188132
2023-06-15

Adaptive control of non-overlapping drive signals

#9
20230179193
2023-06-08

Memory package, semiconductor device, and storage device

#10
20230046725
2023-02-16

Clock mode determination in a memory system

#11
20220038086
2022-02-03

Dual clock signal to pulse-width modulated signal conversion circuit

#12
20220038084
2022-02-03

Digital timer delay line with sub-sample accuracy

#13
20210132799
2021-05-06

Clock mode determination in a memory system

#14
20210111715
2021-04-15

Adaptive control of non-overlapping drive signals

#15
20200110535
2020-04-09

Clock mode determination in a memory system

#16
20190163365
2019-05-30

Clock mode determination in a memory system

#17
20180314424
2018-11-01

Clock mode determination in a memory system

#18
20180234097
2018-08-16

Precision modulation timer (PMT) integrated in a programmable logic device

#19
20170322730
2017-11-09

Clock mode determination in a memory system

#20
20170288655
2017-10-05

Arbitrary delay buffer

#21
20150365082
2015-12-17

Tunable clock system

#22
20150358007
2015-12-10

Delay structure for a memory interface

#23
20150255167
2015-09-10

Clock mode determination in a memory system

#24
20150109039
2015-04-23

Tunable clock system

#25
20140133243
2014-05-15

Clock mode determination in a memory system

#26
20140084979
2014-03-27

Self-adjusting duty cycle tuner

#27
20140009197
2014-01-09

Self-adjusting duty cycle tuner

#28
20110110165
2011-05-12

Clock mode determination in a memory system

#29
20100134169
2010-06-03

Delay circuit

#30
20100097114
2010-04-22

Pulse width modulation circuit and liquid jet printing apparatus

#31
20090167378
2009-07-02

Method and system for providing a power-on reset pulse

#32
20090039927
2009-02-12

Clock mode determination in a memory system

#33
20090002083
2009-01-01

Oscillation Circuit, Power Supply Circuit, Display Device, and Electronic Apparatus

#34
20080309606
2008-12-18

Timing controller counts clock signals to produce a control signal only after a number of clock pulses are counted

#35
20080180182
2008-07-31

Delay unit

#36
20080164929
2008-07-10

Electronic Circuit Wherein an Asynchronous Delay is Realized

#37
20080136485
2008-06-12

DELAY CIRCUIT AND DELAY SYNCHRONIZATION LOOP DEVICE

#38
20080122512
2008-05-29

Digital power-on reset

#39
20080055139
2008-03-06

Digital modulation circuit

#40
20070268049
2007-11-22

Method and system for providing a power-on reset pulse

#41
20070217483
2007-09-20

Spread spectrum block control apparatus and spread spectrum clock generating apparatus

#42
20070200641
2007-08-30

System and method for multiple-phase clock generation

#43
20070194826
2007-08-23

CIRCUIT CAPABLE OF SELF-CORRECTING DELAY TIME AND METHOD THEREOF

#44
20070146523
2007-06-28

Signal generator

#45
20070030045
2007-02-08

Delay circuit and delay synchronization loop device

#46
20070030043
2007-02-08

Delay circuit and delay synchronization loop device

#47
20070030040
2007-02-08

Delay circuit and delay synchronization loop device

#48
20060220721
2006-10-05

Clock delay compensation circuit

#49
20060210006
2006-09-21

Phase generator for introducing phase shift in a signal

#50
20060158238
2006-07-20

Circuit and method of controlling a delay of a semiconductor device

#51
20060132211
2006-06-22

Control adjustable device configurations to induce parameter variations to control parameter skews

#52
20060077011
2006-04-13

Synchronous delay-line amplification technique

#53
20060076997
2006-04-13

Spread spectrum clock generating apparatus

#54
20060066367
2006-03-30

Method and system for providing a power-on reset pulse

#55
20050206426
2005-09-22

Integrated circuit systems and devices having high precision digital delay lines therein

#56
20050184777
2005-08-25

Method and apparatus for an improved timer circuit and pulse width detection

#57
20050179476
2005-08-18

System and method for creating a limited duration clock divider reset

#58
20050088323
2005-04-28

Depression judgment device

#59
20050030682
2005-02-10

Input circuit and method for the operation thereof

#60
20050024107
2005-02-03

Delay circuit and delay synchronization loop device

#61
18623657
2025-09-30

Self-calibration of delay circuits in asynchronous loops

#62
16656269
2020-12-29

Low-power fast-setting delay circuit

#63
16600857
2020-12-01

Adaptive control of non-overlapping drive signals

#64
16205093
2020-03-10

Ring oscillator-based programmable delay line