221507 ⎘
Manipulating of pulses not covered by one of the other main groups of this subclass; Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse; Layout of the delay element using circuits having two logic levels using microprocessors
Static compensation of an active clock edge shift for a duty cycle correction circuit
#2Static compensation of an active clock edge shift for a duty cycle correction circuit
#3Static compensation of an active clock edge shift for a duty cycle correction circuit
#4RC lattice delay