221509 ⎘
Manipulating of pulses not covered by one of the other main groups of this subclass; Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse; Layout of the delay element using circuits having two logic levels using D/A or A/D converters
MEMORY CONTROLLER USING A DIGITAL SIGNAL PROCESSOR IN TRANSMITTERS TO MITIGATE NOISE AND DISTORTION IN MEMORY LINKS
#2TUNING OF DATA INTERFACE TIMING BETWEEN CLOCK DOMAINS
#3TUNING OF DATA INTERFACE TIMING BETWEEN CLOCK DOMAINS
#4Display device and power management chip for the same
#5Optical driving device and optical communication system
#6Method for synchronizing data converters by means of a signal transmitted from one to the next
#7Generating a plurality of clock signals or high-frequency signals
#8RC lattice delay
#9FINE DELAY ADJUSTMENT
#10Phase interpolation apparatus, systems, and methods
#11Phase interpolation apparatus, systems, and methods
#12Method and apparatus for data transfer using a time division multiple frequency scheme supplemented with polarity modulation
#13Data transfer using frequency notching of radio-frequency signals
#14Delay circuit, and testing apparatus
#15Method and apparatus for data transfer using wideband bursts
#16Multiplying delay locked loops with compensation for realignment error