ADJUSTED-FREQUENCY SYNCHRONIZER FOR CLOCK DOMAIN CROSSING

Low-jitter frequency division clock clock circuit

Read clock generation circuit and data processing circuit including the same

Ultrasound imaging system with a transmit pulse sequence generator circuit

Low power tunable reference current generator

Capacitance determination circuit and method for determining a capacitance

Electronic device and electronic system including the same

Regenerative frequency divider

Electronic device and electronic system including the same

Measuring setup and hold times using a virtual delay

Digital counter comprising reduced transition density

Double data rate counter, and analog-to-digital converter and CMOS sensor including the same

Multiple data rate counter, data converter including the same, and image sensor including the same

Inductor-less 50% duty cycle wide-range divide-by-3 circuit

Low power tunable reference voltage generator

Low power tunable reference current generator

Method and apparatus for low jitter distributed clock calibration

System and method for signal mixing based on high order harmonics

System and method for multiple-phase clock generation

Multiple data rate counter, data converter including the same, and image sensor including the same

Method and apparatus for generating frequency divided signals

Frequency Divider Circuit

Counter of semiconductor device

Semiconductor memory device

Semiconductor memory device

Method and apparatus for generating frequency divided signals

Counter outputting count signal having random count value

Shift register and image display apparatus containing the same

Clock frequency divider circuit and method of dividing clock frequency

Synchronous frequency dividers and components therefor

Semiconductor circuit device

Counting device