LATCH CIRCUIT AND METHOD OF OPERATING THE SAME

METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS

CROSS-COUPLED LATCH CHARGE PUMP AS WELL AS A METHOD OF OPERATING SUCH A CROSS-COUPLED LATCH CHARGE PUMP

REDUCED POWER CONSUMPTION COMPUTE-IN-MEMORY SYSTEM, METHOD OF OPERATING SAME

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME

LOW-POWER FLIP FLOP CIRCUIT

METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS

Integrated circuit and method of forming the same

Semiconductor circuit including latch circuit for error correction

DYNAMIC D FLIP-FLOP, REGISTER, CHIP, AND DATA PROCESSING APPARATUS

LATCH CIRCUIT AND METHOD OF OPERATING THE SAME

Flip-flop, master-slave flip-flop, and operating method thereof

Low-power flip flop circuit

Integrated circuit including flip-flop and computing system for designing the integrated circuit

Method for forming a timing circuit arrangements for flip-flops

Latch circuit, flip-flop circuit including the same

Timing circuit arrangements for flip-flops

Customizable backup and restore from nonvolatile logic array

High-speed flip flop circuit including delay circuit

Latch circuit, flip-flop circuit including the same

LOW-POWER FLIP FLOP CIRCUIT

Flip-flop, master-slave flip-flop, and operating method thereof

Flip-flop

Semiconductor integrated circuit

Clock buffering to reduce memory hold time

Processing device with nonvolatile logic array backup

Flip-flop with a metal programmable initialization logic state

Vertical field-effect transistor (VFET) devices including latches having cross-couple structure

State retention circuit that retains data storage element state during power reduction mode

Ultra-Low Power Static State Flip Flop

Low-power flip flop circuit

Level shifter circuit, corresponding device and method

Processing device with nonvolatile logic array backup

Method to synchronize integrated circuits fulfilling functional safety requirements

Tunnel field-effect transistor (TFET) based high-density and low-power sequential

Ultra-low power static state flip flop

High-definition multimedia interface apparatus capable of communication with slave/master apparatus utilizing the same HDMI port and method for controlling the same

Time borrowing flip-flop with clock gating scan multiplexer

Priority based backup in nonvolatile logic arrays

Non-volatile memory circuit

Low power flip flop circuit

Shared keeper and footer flip-flop

Circuit and method for checking the integrity of a control signal

Time borrowing flip-flop with clock gating scan multiplexer

Current-controlled CMOS logic family

Ramp based clock synchronization for stackable circuits

Latch circuitry

Nonvolatile logic array based computing over inconsistent power supply

Configuration bit sequencing control of nonvolatile domain and array wakeup and backup

Current steering phase control for CML circuits

Area-optimized retention flop implementation

Power multiplexing with flip-flops

SCAN SEQUENTIAL ELEMENT DEVICE

Flip-flop structure

Area-delay-power efficient multibit flip-flop

Flip-flop circuit with latch bypass

Customizable backup and restore from nonvolatile logic array

Data holding circuit including latch circuit and storing circuit having MTJ elements and data recovery method

Integrated circuit with internal and external voltage regulators

Current-controlled CMOS logic family

Three dimensional integrated circuit and method for controlling the same

Scannable flop with a single storage element

Positive edge flip-flop with dual-port slave latch

Semiconductor circuit and method of operating the same

Negative edge reset flip-flop with dual-port slave latch

Negative edge preset reset flip-flop with dual-port slave latch

MCML retention flip-flop/latch for low power applications

Measured value transmitting device

Processing device with nonvolatile logic array backup

Priority based backup in nonvolatile logic arrays

Current-controlled CMOS logic family

Differential latch, differential flip-flop, LSI, differential latch configuration method, and differential flip-flop configuration method

Differential latch, differential flip-flop, LSI, differential latch configuration method, and differential flip-flop configuration method

Digital logic circuit, shift register and active matrix device

Latch module and frequency divider

Semiconductor device

Current-controlled CMOS logic family

Current-controlled CMOS logic family

Compound logic flip-flop having a plurality of input stages

Data retention flip flop for low power applications

Current-controlled CMOS logic family

SEMICONDUCTOR DEVICE

Semiconductor integrated circuit

Flip-flop having logic state retention during a power down mode and method therefor

System and method for effectively implementing an IQ generator

Digital single event transient hardened register using adaptive hold

Differential latch, differential flip-flop, LSI, differential latch configuration method, and differential flip-flop configuration method

Logic circuit

Sequential circuit design for radiation hardened multiple voltage integrated circuits

METHOD AND APPARATUS FOR A LOW STANDBY-POWER FLIP-FLOP

Current-controlled CMOS logic family

Current-controlled CMOS logic family

Data-signal-recovery circuit, data-signal-characterizing circuit, and related integrated circuits, systems, and methods

Differential master/slave CML latch

Current-controlled CMOS logic family

Synchronous data serialization circuit

Flip-flop with a metal programmable initialization logic state

DFE hysteresis compensation (specific)

State retention circuit that retains data storage element state during power reduction mode

Shared keeper and footer flip-flop

Low power flip-flop circuit

Unified retention flip-flop architecture and control

Dynamic flip-flop and multiplexer for sub-rate clock data serializer