DYNAMIC HIGH-SPEED FLIP FLOP

ROBUST SINGLE EVENT UPSET (SEU) TOLERANT HIGH-PERFORMANCE FLIP-FLOP

RESETTABLE LEVEL SHIFTING LATCH

INTEGRATED CIRCUIT DEVICE, METHOD AND SYSTEM

METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS

LOW AREA AND POWER MULTI-BIT FLIP-FLOP

Flip Flop Circuit

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME

FLIP-FLOP CIRCUIT AND METHOD

INTEGRATED CIRCUIT HAVING LATCH WITH TRANSISTORS OF DIFFERENT GATE WIDTHS

LEAKAGE-FREE DUMMY CELL FOR SEMICONDUCTOR DEVICES

METHODS AND APPARATUS TO PERFORM CLOCK GATING

LOW AREA AND POWER MULTI-BIT FLIP-FLOP

FLIP-FLOPS HAVING STRONG TRANSISTORS AND WEAK TRANSISTORS

SYNCHRONIZER FLIP-FLOP CIRCUIT

LOW POWER FLIP-FLOP AND INTEGRATED CIRCUIT INCLUDING THE SAME

Flip-flops having strong transistors and weak transistors

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME

LEAKAGE-FREE DUMMY CELL FOR SEMICONDUCTOR DEVICES

Circuits, devices, and methods for reducing flip-flop short-circuit currents

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME

FLIP-FLOP CIRCUIT AND METHOD

LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY

INTEGRATED CIRCUIT HAVING LATCH WITH TRANSISTORS OF DIFFERENT GATE WIDTHS

FINE GRAIN POWER GATING

LOW-POWER FLIP FLOP CIRCUIT

METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS

INTEGRATED CIRCUIT DEVICE, METHOD AND SYSTEM

Integrated circuit and method of forming the same

DATA FLIP-FLOP CIRCUIT OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME

Integrated circuit and method of forming the same

Integrated circuit having latch with transistors of different gate widths

System and method for reducing circuit elements in high-performance flip-flops

Semiconductor device and semiconductor system having the same

Flip Flop Circuit

Flip Flop Circuit

Circuits and methods for generating data outputs utilized shared clock-activated transistors

Multi-bit flip-flop circuit with reduced area and reduced wire complexity

Process for scan chain in a memory

Integrated circuit device, method and system

Flip-flop circuit and method

Dynamic D flip-flop with an inverted output

Data retention circuit and method

Scan chain for memory with reduced power consumption

Semiconductor integrated circuit comprising master chip with first buffer circuit and slave chiip with second buffer circuit

Flip-flop circuit and asynchronous receiving circuit

Low-power flip flop circuit

Data multiplexer single phase flip-flop

Method for forming a timing circuit arrangements for flip-flops

Timing circuit arrangements for flip-flops

LOW POWER SEQUENTIAL CIRCUIT APPARATUS

Low-power flip-flop architecture with high-speed transmission gates

Flip-flop circuit with glitch protection

High performance fast Mux-D scan flip-flop

Semiconductor device

Semiconductor device

SEMICONDUCTOR DEVICE

Radiation hardened flip-flop circuit for mitigating single event transients

Fault resilient flip-flop with balanced topology and negative feedback

True single-phase clock (TSPC) NAND-based reset flip-flop

Semiconductor device without a break region

Complementary clock gate and low power flip-flop circuit including same

Flip flop circuit

Shift register, display device, and method for controlling shift register

Data holding circuit

Flip-flop with delineated layout for reduced footprint

Master-slave D flip-flop

RADIATION-HARDENED D FLIP-FLOP CIRCUIT

D-type flip-flop circuit

Semiconductor device including standard cell

Pre-discharging based flip-flop with a negative setup time

LOW-POWER FLIP FLOP CIRCUIT

HYBRID STANDARD CELL AND METHOD OF DESIGNING INTEGRATED CIRCUIT USING THE SAME

Semiconductor device

Semiconductor device

SRAM LOW-POWER WRITE DRIVER

Cell of transmission gate free circuit and integrated circuit layout including the same

Semiconductor circuit and semiconductor circuit layout system

Low-power scan flip-flop

Failsafe device

Semiconductor device

Semiconductor device without a break region

Power supply apparatus and master power supply circuit, slave power supply circuit and control method thereof

Flip-flop with delineated layout for reduced footprint

Semiconductor device

D FLIP-FLOPS WITH LOW CLOCK DISSIPATION POWER

Vertical field-effect transistor (VFET) devices including latches having cross-couple structure

Scan flip-flop and scan test circuit including the same

Flip-flop

Low power flip-flop circuit

Radiation-hardened D flip-flop circuit

Flip-flop including 3-state inverter

State retention circuit that retains data storage element state during power reduction mode

Ultra-Low Power Static State Flip Flop

Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections

Low-power flip flop circuit

Semiconductor device and memory system for combining reversed-phase data

Low voltage, master-slave flip-flop

Master-slave flip flop

Flip-flop with delineated layout for reduced footprint

Semiconductor device

Cell of transmission gate free circuit and integrated circuit layout including the same

Multiple mode device implementation for programmable logic devices

Apparatus and method for clock signal frequency division using self-resetting, low power, linear feedback shift register (LFSR)

Master-slave flip flop

Flop circuit with integrated clock gating circuit

Flip-flop with single pre-charge node

Tunnel field-effect transistor (TFET) based high-density and low-power sequential

Scan output flip-flops

Semiconductor device

Ultra-low power static state flip flop

Frequency divider

Flip-flop

Master-slave level shifter array architecture with pre-defined power-up states

High performance low retention mode leakage flip-flop

Shift register utilizing latches controlled by dual non-overlapping clocks

Level-shifter circuits and methods of using the same

Bidirectional AC/DC H-bridge power converter

Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same

Retention flip-flop circuits for low power applications

Non-volatile memory circuit

Low power flip flop circuit

Shared keeper and footer flip-flop

Flip-flop

Flip-flop

Flip-flop and semiconductor system including the same

LOW POWER MASTER-SLAVE FLIP-FLOP

Shift register capable of defending against DPA attack

Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit

Method for managing the operation of a low-complexity synchronous retention flip-flop circuit, and corresponding circuit

Low clock supply voltage interruptible sequential

Flip-flop including 3-state inverter

Systems and methods for non-volatile flip flops

Reduced power set-reset latch based flip-flop

Buffer, and multiphase clock generator, semiconductor apparatus and system using the same

Scan flip-flop and scan test circuit including the same

Multi-stage frequency dividers and poly-phase signal generators

Power efficient high speed latch circuits and systems

Multiple mode device implementation for programmable logic devices

Flexible ripple mode device implementation for programmable logic devices

Flip-flop with delineated layout for reduced footprint

Semiconductor integrated circuit

Integrated circuit and design method for same

Low core power leakage structure in IO receiver during IO power down

Multi-bit data flip-flop with scan initialization

METHOD TO CONTROL D-FF CIRCUIT

Tri-state inverter, D latch and master-slave flip-flop comprising TFETs

Flip flop using dual inverter feedback

Electronic latch circuit and a generic multi-phase signal generator

Low-power, small-area, high-speed master-slave flip-flop circuits and devices including same

Semiconductor device without a break region

Semiconductor device comprising low power retention flip-flop

Semiconductor device including retention reset flip-flop

D flip-flop and signal driving method

Clock gated flip-flop

Ultra-low power static state flip flop

Skew-tolerant flip-flop

Tunnel field-effect transistor (TFET) based high-density and low-power sequential

Area efficient flip-flop with improved scan hold-margin

Digital circuit and method for manufacturing a digital circuit

Semiconductor integrated circuits

Semiconductor integrated circuit

Multi-bit flip-flop with shared clock switch

Latch and D Flip-Flop

Multi-bit flip-flops and scan chain circuits

Compact design of scan latch

Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Area efficient multi bit flip flop topologies

FLIP-FLOP CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Flip-flop structure

Area-delay-power efficient multibit flip-flop

MULTI-LEVEL CONVERSION FLIP-FLOP CIRCUITS FOR MULTI-POWER DOMAIN INTEGRATED CIRCUITS (ICs) AND RELATED METHODS

Data register for radiation hard applications

Common N-well state retention flip-flop

Semiconductor device

Flip-flop circuit with latch bypass

Three dimensional logic circuit

Low-power retention flip-flops

Low area enable flip-flop

Low-power, small-area, high-speed master-slave flip-flop circuits and devices including same

Logic circuit and semiconductor device including logic circuit

Non-volatile semiconductor memory device with temporary data retention cells and control method thereof

High-speed flip-flop with robust scan-in path hold time

Synchroniser flip-flop

Data storage element and signal processing method

Flip-flop cell with configurable delay

Scan flip-flop and scan test circuit including the same

Low area flip-flop with a shared inverter

Fault resistant flip-flop

Low swing flip-flop with reduced leakage slave latch

Clock gated flip-flop

Low leakage shadow latch-based multi-threshold CMOS sequential circuit

Flip-flop for reducing dynamic power

Low power flip-flop element with gated clock

Multiple mode device implementation for programmable logic devices

Flexible ripple mode device implementation for programmable logic devices

Shared logic for multiple registers with asynchronous initialization

FLIP-FLOP CIRCUIT

Multi-bit standard cells for consolidating transistors with selective sourcing

Voltage level shifter circuit, system, and method for wide supply voltage applications

Low power master-slave flip-flop

Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Single phase GSHE-MTJ non-volatile flip-flop

Three-phase GSHE-MTJ non-volatile flip-flop

Master-slave flip-flop circuit and method of operating the master-slave flip-flop circuit

Circuit for improving clock rates in high speed electronic circuits using feedback based flip-flops

Semiconductor integrated circuit configured to drive a liquid crystal display

Redundant clock transition tolerant latch circuit

Latch circuit

Low power clock gated flip-flops

Scannable flop with a single storage element

Negative edge flip-flop with dual-port slave latch

Positive edge flip-flop with dual-port slave latch

Semiconductor device

Positive edge preset reset flip-flop with dual-port slave latch

Circuit for reducing negative bias temperature instability

Flip-flop with reduced retention voltage

Flip-flop circuit with resistive poly routing

Apparatus and methods for loss of signal detection

Master-slave flip-flop with low power consumption

NEGATIVE EDGE PRESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH

Negative edge reset flip-flop with dual-port slave latch

Flip-flop circuit

Phase comparison circuit and data receiving unit

Sequential state elements radiation hardened by design

Flip-flop circuit and semiconductor device

High density flip-flop with asynchronous reset

MASTER SLAVE FLIP-FLOP WITH LOW POWER CONSUMPTION

Low-hysteresis high-speed differential sampler

Semi-dynamic flip-flop with partially floating evaluation window

Multi-threading flip-flop circuit

Device with a data retention mode and a data processing mode

Method and System for High Speed, Low Power and Small Flip-Flops

Semiconductor device

Delay latch circuit and delay flip-flop

Scannable flip-flop with hold time improvements

Semiconductor integrated circuit

Master-slave flip-flop with timing error correction

Master-slave flip-flop circuit

Clock state independent retention master-slave flip-flop

Depletion-mode MOSFET circuit and applications

Multi-threshold complementary metal-oxide semiconductor master slave flip-flop

Circuit for reducing negative bias temperature instability

SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE RECORDING MEDIUM

Retention flip-flop

FLIP-FLOP CIRCUIT AND FREQUENCY DIVIDING CIRCUIT

Flip-flop with single clock phase and with reduced dynamic power

Semiconductor integrated circuit

Registers with reduced voltage clocks

Semiconductor device

Low latency synchronizer circuit

Leakage power optimized structure

Scanning-capable latch device, scan chain device, and scanning method with latch circuits

Semiconductor device

LATCH WITH SINGLE CLOCKED DEVICE

Latch with clocked devices

Semiconductor device

Level shifter flip-flop

Latch and DFF design with improved soft error rate and a method of operating a DFF

Double-triggered logic circuit

Functional frequency testing of integrated circuits

Functional frequency testing of integrated circuits

Low power and soft error hardened dual edge triggered flip flop

DUAL MODE EDGE TRIGGERED FLIP-FLOP

Low Power and Full Rail-to-Rail Swing Pseudo CML Latch

High-speed low-power latches

Optimization of library slew ratio based circuit

Low power flip flop through partially gated slave clock

Programmable sample clock for empirical setup time selection

DATA RETENTION DEVICE FOR MULTIPLE POWER DOMAINS

Flip-Flop Capable of Operating at High-Speed

Semiconductor integrated circuit

DYNAMIC SEMICONDUCTOR DEVICE

High performance CMOS radio frequency receiver

INTEGRATED CIRCUITS HAVING DEVICES IN ADJACENT STANDARD CELLS COUPLED BY THE GATE ELECTRODE LAYER

SEMICONDUCTOR DEVICE

Design structure for CMOS differential rail-to-rail latch circuits

MTCMOS FLIP-FLOP WITH RETENTION FUNCTION

Latch device having low-power data retention

MASTER-SLAVE CIRCUIT AND CONTROL METHOD OF THE SAME

Slave latch controlled retention flop with lower leakage and higher performance

Semiconductor integrated circuit device

Master-slave type flip-flop circuit

Logic circuit including a plurality of master-slave flip-flop circuits

Data pipeline with large tuning range of clock signals

Flip-flop and shift register

Push-Pull Pulse Register Circuit

LCD driving method using self-masking, and masking circuit and asymmetric latches thereof

Semiconductor integrated circuit with flip-flop circuits mounted thereon

Master-slave type flip-flop circuit and latch circuit

COMPLEMENTARY OUTPUT FLIP FLOP

Method of Phase Noise Reduction in a Soi Type Master-Slave Circuit

CMOS DIFFERENTIAL RAIL-TO-RAIL LATCH CIRCUITS

Depletion-mode MOSFET circuit and applications

Semiconductor integrated circuit

FLIP-FLOP CIRCUIT

Storage device having low power mode and methods thereof

Flip-flop circuit

FLIP-FLOP CIRCUIT

FLIP-FLOP HAVING IMPROVED SET-UP TIME AND METHOD USED WITH