ClassID:

221548

H03K5/15046 - CPC Classification

Classification description:

Manipulating of pulses not covered by one of the other main groups of this subclass; Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line

Recent Application in this class:
#1
20250158798
2025-05-15

Synchronising Devices Using Clock Signal Delay Comparison

#2
20200259631
2020-08-13

Synchronizing devices using clock signal delay comparison

#3
20200235726
2020-07-23

Measurement, calibration and tuning of memory bus duty cycle

#4
20180367130
2018-12-20

Multi-phase clock generator

#5
20180302067
2018-10-18

Circuit for meeting setup and hold times of a control signal with respect to a clock

#6
20180123575
2018-05-03

Quadrature clock generating mechanism of communication system transmitter

#7
20170346467
2017-11-30

Delay line with short recovery time

#8
20170141736
2017-05-18

Broadband envelope tracking

#9
20170070338
2017-03-09

Synchronising devices using clock signal delay comparison

#10
20160191084
2016-06-30

Data transmitter, data receiver and smart device using the same

#11
20130015898
2013-01-17

Frequency-doubling delay locked loop

#12
20120213309
2012-08-23

Phase adjusting device and camera

#13
20100327983
2010-12-30

Ring oscillator

#14
20100259435
2010-10-14

Delay circuit

#15
20100225370
2010-09-09

Frequency-doubling delay locked loop

#16
20090179677
2009-07-16

CIRCUIT FOR GENERATING OVERLAPPING SIGNALS

#17
20090039931
2009-02-12

Frequency-doubling delay locked loop

#18
20070170971
2007-07-26

SIGNAL TRANSMITTING CIRCUIT

#19
20060261866
2006-11-23

Frequency-doubling delay locked loop

#20
20060083341
2006-04-20

System and method to reduce jitter

#21
20050047445
2005-03-03

Clock signal distribution network and method

#22
16244924
2020-04-14

Measurement, calibration and tuning of memory bus duty cycle

#23
15485781
2018-02-20

Digital to analog conversion using semi-digital FIR filter

#24
15339490
2019-02-05

Synchronous N pulse burst generator

#25
15174871
2017-03-21

Method and apparatus for multi-rate clock generation