LOW-POWER LOW-AREA DEADTIME GENERATOR

MULTI-PHASE SIGNAL GENERATION

Multi-phase signal generation

STAGGERING SIGNAL GENERATION CIRCUIT AND INTEGRATED CHIP

Multi-phase signal generation

Phase error correction for clock signals

Clock generation circuit and charge pumping system

Multi-phase signal generation

Signal transmission device and drive device

Increasing efficiency of a switched mode power converter

Clock generator

Clock generation circuit and charge pumping system

Shift register utilizing latches controlled by dual non-overlapping clocks

Double compression avoidance

Double compression avoidance

Circuits for optimizing skew and duty cycle distortion between two signals

Adaptive control of the non-overlap time of power switches

Shift register utilizing latches controlled by dual non-overlapping clocks

Phase interpolator, apparatus for phase interpolation, digital-to-time converter, and methods for phase interpolation

Oscillator and clock generator

Dead time compensation

PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications

Clock generation circuit and charge pumping system

Electronic circuit for controlling a half H-bridge

Dead time circuit for a switching circuit and a switching amplifier

Circuit and method for generating clock-signals

Clock generation circuit

Dead time adjusting circuit

Memory apparatus, charge pump circuit and voltage pumping method thereof

Apparatuses and methods for providing clock signals

Gate driver and control method thereof

DC voltage generation circuit and pulse generation circuit thereof

DC voltage generation circuit and pulse generation circuit thereof

Apparatuses and methods for providing clock signals

Anti-shoot-through automatic multiple feedback gate drive control circuit

Switch driving circuit

Complementary output generator module

System and method for bootstrapping a switch driver

Non-overlapping clock generator circuit and method

Time difference amplifier and amplification method using slew rate control

Relaxation oscillator circuit including two clock generator subcircuits having same configuration operating alternately

Non-overlap circuit

High temperature half bridge gate driver

Time-to-digital conversion stage and time-to-digital converter including the same

Control circuit arrangement for pulse-width modulated DC/DC converters and method for controlling a pulse-width modulated converter

Pre-emphasis circuit and differential current signaling system having the same

Non-overlapping clock generation

System and method for bootstrapping a switch driver

Dead-time generating circuit and motor control apparatus

Delay block for controlling a dead time of a switching voltage regulator

Analog-to-digital converter timing circuits

Clock generation circuit and integrated circuit

Temperature-stable oscillator circuit having frequency-to-current feedback

Dead-time detecting circuit for inductive load and modulation circuit using the same

ARITHMETIC CIRCUIT AND POWER SAVING METHOD

Systems and methods to minimize startup transients in class-D amplifiers

Techniques for non-overlapping clock generation

Oscillation drive device, physical quantity measurement device and electronic apparatus

Clock driver circuit

Clock generation circuit and integrated circuit

Clock pulse generating circuit

Electronic circuit

Power amplifier

CLOCK SIGNAL GENERATION APPARATUS AND DISCRETE-TIME CIRCUIT

Clock signal generation apparatus

Ratio asymmetric inverters, and apparatus including one or more ratio asymmetric inverters

Pulse width modulation dead time compensation method and apparatus

Output buffer for an electronic device

High side boosted gate drive circuit

Clock generator

Low voltage synchronous oscillator for DC-DC converter

Output buffer circuit

Output circuit

Systems and methods to minimize startup transients in class D amplifiers

Clock pulse generating circuit

Delay circuit with reference pulse generator to reduce variation in delay time

BIAS SWITCHING CIRCUIT

Single signal-to-differential signal converter and converting method

LOW POWER OSCILLATOR

Dynamic dual output latch

GATE DRIVE CIRCUIT

Digital pulse frequency/pulse amplitude (DPFM/DPAM) controller for low-power switching-power supplies

Clock control circuit and semiconductor integrated circuit using the same

Clock generator with programmable non-overlapping-clock-edge capability

Driver circuit

Phase splitters

Non-overlapping multi-stage clock generator system

Complementary output inverter

Low-power consumption high-voltage CMOS driving circuit

SEMICONDUCTOR DEVICE

Clock signal generating device, generating method, and signal processing device

Input/output logical circuit

Non-latching enveloping curves generator

Digital storage element architecture comprising dual scan clocks and preset functionality

Digital storage element architecture comprising dual scan clocks and reset functionality

Dead time control circuit capable of adjusting temperature characteristics of dead time

Digital differential amplification control device

Method and apparatus to generate break before make signals for high speed TTL driver

Method and apparatus for generating non-skewed complementary signals through interpolation

Single to dual non-overlapping converter

Gate driver with programmable dead-time insertion

Clock generator with programmable non-overlapping-clock-edge capability

Logical circuit

Buffer circuit, buffer tree, and semiconductor device

Driver circuit

Three-transistor NAND and NOR gates for two-phase clock generators

Multi-phase clock signal generators and methods of generating multi-phase clock signals

Linearized time amplifier architecture for sub-picosecond resolution

Adaptively controlled duty cycle clock generation circuit

Method of implementing a differential integrating phase interpolator

System and techniques for repeating differential signals

Gm-C filter and multi-phase clock circuit