Method and apparatus for timing and event processing in wireless systems

Methods and arrangements for link power reduction

System and method for pre-defined wake-up of high speed serial link

Crystal oscillator emulator

High speed level shifter circuit and circuit using same

Clock data recovery circuitry associated with programmable logic device circuitry

Method, circuit and system for detecting a locked state of a clock synchronization circuit

Low power charge pump

Crystal oscillator emulator

Crystal oscillator emulator

Crystal oscillator emulator

Configurable multi-modulus frequency divider for multi-mode mobile communication devices

PLL apparatus with power saving mode and method for implementing the same

Delay-locked loops for semiconductor devices and methods of controlling the same

Method and apparatus for fast locking of a clock generating circuit

Charge pump circuit with power management

Delayed Locked Loop Circuit

Tri-stating a phase locked loop to conserve power

Delay-locked loop circuit with variable bias voltages and method of clock synchronization for a semiconductor memory device

Internal voltage generator and internal clock generator including the same, and internal voltage generating method thereof

Phase locked loop with power distribution

Two-system PLL frequency synthesizer

PLL circuit having reduced pull-in time

Methods and apparatuses for changing capacitance

Delay stage-interweaved analog DLL/PLL

Delay stage-interweaved analog DLL/PLL

Delay stage-interweaved analog DLL/PLL

Delay line off-state control with power reduction

Delay stage-interweaved analog DLL/PLL

Frequency synthesizer and method for operating a frequency synthesizer

Frequency synthesizer and method for operating a frequency synthesizer

Internal supply voltage generator for delay locked loop circuit

System and method for achieving low power standby and fast relock for digital phase lock loop

Configurable delay line circuit

Methods and arrangements for link power reduction

Delayed locked loops and methods of driving the same

Apparatus for generating multiple clock signals of different frequency characteristics

DTC nonlinearity correction

Low-power, reduced-area VCO design with power supply noise rejection

Low-power fractional analog PLL without feedback divider

Phase locked loop with phase error signal used to control effective impedance

Spur cancellation in a PLL system with an automatically updated target spur frequency

Clocking architecture for DVFS with low-frequency DLL locking

Data and clock recovery circuit

Integrated circuit with oscillator signal based on switched-resistance circuitry

Adaptive time-to-digital converter and method

Delay-locked loop with large tuning range

Digital locking loop circuit and method of operation

Electronic device with a timing adjustment mechanism

Phase locked loop with switched-component loop filter

Frequency locked loop with multi-bit sampler

Background calibration for real-time clock systems

Ultra-low-power injection locked oscillator for IQ clock generation

Frequency-agile clock generator

Digital locking loop circuit and method of operation

Charge pump circuits for clock and data recovery

Dual-mode low-power low-jitter noise phased locked loop system

PLL with accelerated frequency lock

Low power digital-to-analog converter (DAC)-based frequency synthesizer

Performance indicator for phase locked loops

Supply voltage tracking clock generator in adaptive clock distribution systems

Methods and apparatus for reducing power in clock distribution networks

High-gain locked-loop phase detector

Integrated circuits having multiple digitally-controlled oscillators (DCOs) therein that are slaved to the same loop filter

Digital delay-locked loop (DLL) training

Low power wireless receiver for congested networks operating with beacon frames

Frequency-agile clock multiplier

Generating signals with accurate quarter-cycle intervals using digital delay locked loop

A-priori-probability-phase-estimation for digital phase-locked loops

Phase locked loop circuitry having switched resistor loop filter circuitry, and methods of operating same

Phase-locked loop and method for controlling the same

Digital delay-locked loop circuit using phase-inversion algorithm and method for controlling the same

Clock generator

Clock multiplier with dynamically tuned lock range

Cross-domain enablement method and electronic apparatus

Techniques for generating fractional periodic signals

Hybrid phase-locked loops

Multi-rate control loop for a digital phase locked loop