PHASE-LOCKED LOOP CIRCUIT, PHASE-LOCKING METHOD, AND FREQUENCY SYNTHESIZER

CLOCK DIVIDER AND METHOD OF CONTROLLING SAME

CLOCK SIGNAL GENERATION CIRCUIT AND CLOCK SIGNAL GENERATION METHOD THEREOF

ALL DIGITAL PHASE-LOCKED LOOP CIRCUIT

PHASE-LOCKED LOOP CIRCUIT

VOLTAGE SCALING SYSTEM USED FOR REDUCING POWER CONSUMPTION

POWER CONSERVING CLOCK CIRCUIT WITH FAST START-UP

SIGNAL PROCESSING SYSTEMS AND METHODS

Frequency-regulated oscillator circuit

Compensation Technique for the Nonlinear Behavior of Digitally-Controlled Oscillator (DCO) Gain

VOLTAGE SCALING SYSTEM USED FOR REDUCING POWER CONSUMPTION

PROCESSOR-BASED SYSTEM EMPLOYING CONFIGURABLE LOCAL FREQUENCY THROTTLING MANAGEMENT TO MANAGE POWER DEMAND AND CONSUMPTION, AND RELATED METHODS

Signal processing systems and methods

Transceiver circuit and control method of frequency synthesizer

Millimeter-wave scalable PLL-coupled array for phased-array applications

Oscillator circuit

Method for enhancing the starting of an oscillator of a super-regenerative receiver, and receiver for implementing the method

PHASE LOCK LOOP WITH AN ADAPTIVE LOOP FILTER

Phase-locked loop circuit and method for controlling the same

Clock circuit in a processor integrated circuit

Phase-locked loop circuit, configuration method therefor, and communication apparatus

Signal processing systems and methods

Compensation technique for the nonlinear behavior of digitally-controlled oscillator (DCO) gain

Processor-based system employing configurable local frequency throttling management to manage power demand and consumption, and related methods

ULTRASOUND DEVICE CIRCUITRY INCLUDING PHASE-LOCKED LOOP CIRCUITRY AND METHODS OF OPERATING THE SAME

Operating clock generator and reference clock gating circuit

Millimeter-wave scalable PLL-coupled array for phased-array applications

Integrated circuit with high-speed clock bypass before reset

Reference free and temperature independent voltage-to-digital converter

Time-to-digital converters with low area and low power consumption

Electronic devices for controlling clock generation

Correction signaling between lanes in multi-chip-modules

Transmitter with reduced VCO pulling

Integrated circuit with high-speed clock bypass before reset

Compensation technique for the nonlinear behavior of digitally-controlled oscillator (DCO) gain

Near field communication method and transceiver with clock recovery

DPLL restart without frequency overshoot

Oscillator calibration from over-the air signals

Power supply for voltage controlled oscillators with automatic gain control

Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit

Low-power, low-noise millimeter wavelength frequency synthesizer

Clock generator for adjusting jitter characteristics and operation power, semiconductor device including the clock generator, and operating method of the clock generator

Signal processing systems and methods

Oscillator circuit arrangement

Signal processing systems and methods

CLOCK AND DATA RECOVERY CIRCUIT, MEMORY STORAGE DEVICE AND FLASH MEMORY CONTROLLER

Compensation technique for the nonlinear behavior of digitally-controlled oscillator (DCO) gain

Phase locked loop circuits, clock signal generators comprising digital-to-time convert circuits, operating methods thereof and wireless communication devices

Method and apparatus for source-synchronous signaling

Electronic device with a timing adjustment mechanism

Adaptive time-to-digital converter and method

System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL)

Fast wakeup for crystal oscillator

Reception apparatus with clock failure recovery and transmission system including the same

Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit

Voltage droop monitoring circuits, system-on chips and methods of operating the system-on chips

Phase-locked loop and delay-locked loop

Proactive clock gating system to mitigate supply voltage droops

Charge pump circuits for clock and data recovery

Phase and frequency detection method and circuit

Electronic device with a timing adjustment mechanism

Power supply for voltage controlled oscillators with automatic gain control

Dual mode power supply for voltage controlled oscillators

Compact phase-locked loop with low jitter and reference spurs

Systems and methods for power conservation in a phase locked loop (PLL)

Fast wakeup for crystal oscillator

Using a burn-in operational amplifier for a phased locked loop regulator

Oscillator calibration from over-the-air signals for low power frequency/time references wireless radios

PLL with Lock-in Frequency Controller

PLL with phase range extension

Phase accumulator with improved accuracy

Frequency generator and method for generating frequency

Phase control device and method for multi-resonance system

Phase locked loop circuits, clock signal generators comprising digital-to-time convert circuits, operating methods thereof and wireless communication devices

PLL circuit and CDR apparatus

Clock generator, phase locked loop, apparatus, method and computer program for generating a clock signal, transceiver, and mobile terminal

Method and apparatus for source-synchronous signaling

System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL)

Non-linear spread spectrum profile generator using linear combination

Locked loop circuit with configurable second error input

Clock and data recovery (CDR) circuit

Spread spectrum clock generation apparatus and method, and display device and touch display device

Frequency locked loop with fast reaction time

Phase-locked loop and delay-locked loop

Memory device and method of operating the same for latency control

Phase locked loop and control method therefor

Semiconductor circuit

Compensation technique for the nonlinear behavior of digitally-controlled oscillator (DCO) gain

Digital frequency-division phase-locked loop

SerDes with adaptive clock data recovery

Injection locked oscillator system and processes

Oscillator based sensor interface circuit

Adaptive clocking scheme

Wireless charging system for using frequency control

Fraction-N digital PLL capable of canceling quantization noise from sigma-delta modulator

Feedforward phase noise compensation

Programable immediate frequency change for digital phase locked loop

Phase-locked-loop architecture

Digital fast lock for phase-locked loops

Phase locked loops having decoupled integral and proportional paths

Fractional-N PLL with sleep modes

METHOD AND DRIVER CIRCUIT FOR RESONANT ANTENNA CIRCUIT

Fractional PLLs with low correlation

Method and apparatus for source-synchronous signaling

Digital, reconfigurable frequency and delay generator with phase measurement

Frequency based bias voltage scaling for phase locked loops

Clock signal and supply voltage variation tracking

Device and method for multiple reference system timer

High order hybrid phase locked loop with digital scheme for jitter suppression

Semiconductor device and PLL circuit

Receiver, radio communication device, and radio communication method

Transceiver using technique for improvement of phase noise and switching of phase lock loop (PLL)

Voltage controlled oscillator and phase locked loop comprising the same

Detector generating a displacement signal by injection locking and injection pulling

Frequency synthesizer with injection locked oscillator

Non-linear spread spectrum profile generator using linear combination

Auto frequency calibration method

Method and circuitry for generating trigger signal and associated non-transitory computer program product

Clock and data recovery circuit module and phase lock method

Phase lock method

LEAKAGE COMPENSATION CIRCUIT FOR PHASE-LOCKED LOOP (PLL) LARGE THIN OXIDE CAPACITORS

Clock signal and supply voltage variation tracking

Digital phase controlled delay circuit

Clock generation system with dynamic distribution bypass mode

Memory storage device having clock and data recovery circuit

Phase-locked loop with lower power charge pump

Detector generating a displacement signal by injection locking and injection pulling

Low phase noise frequency divider

Power generating circuit, frequency generating circuit and frequency control system

Apparatuses, methods, and systems for glitch-free clock switching

Receiving device

Methods and apparatuses for adaptive dynamic voltage control for optimizing energy per operation per a given target speed

Leakage compensation circuit for phase-locked loop (PLL) large thin oxide capacitors

Methods and systems for clocking a physical layer interface

Constant voltage circuit and oscillation device

Adaptive clocking scheme

Feedback loop frequency synthesizer device

Closed loop clock signal generator with multiple reference clocks

Ultra-low power transmitter applied in multi-channel frequency shift (FSK) communication

Readout system

Digital phase controlled delay circuit

Digital phase-locked loop and method of operating the same

Modulation circuit and operating method thereof

Fractional-N phase-locked loop

Multi-channel delay locked loop

Systems and methods for frequency domain calibration and characterization

Fractional N-PLL circuit, oscillator, electronic device, and moving object

Digitally controlled oscillator

Fractional-N frequency synthesizer incorporating cyclic digital-to-time and time-to-digital circuit pair

Fractional-N all digital phase locked loop incorporating look ahead time to digital converter

Split transformer based digitally controlled oscillator and DC-coupled buffer circuit therefor

Split transformer based LC-tank digitally controlled oscillator

Delay-locked loop arrangement and method for operating a delay-locked loop circuit

Phase-locked loop (PLL)

Semiconductor device

Edge generator-based phase locked loop reference clock generator for automated test system

VARIABLE DELAY COMPONENT RING OSCILLATOR WITH PHASE SHIFTING SELECT SWITCH

High-order sigma delta for a divider-less digital phase-locked loop

Phase lock loop with cascade tracking filters for synchronizing an electric grid

AFLL with increased timing margin

Semiconductor device, semiconductor system and method for operating semiconductor device

Oscillator crosstalk compensation

All-digital phase-locked loop (ADPLL)

PLL with across-stage controlled DCO

Clock generation circuit with dual phase-locked loops

Method and apparatus for calibrating output frequency of oscillator

Phase-locked loop circuit including voltage down converter consisting of passive element

Delay locked loop, method of operating the same, and memory system including the same

Delay locked loop and semiconductor apparatus

Semiconductor device

Apparatus and methods for phase-locked loop startup operation

Clock generating circuit, semiconductor device including the same, and data processing system

Oscillation circuit, oscillator, fractional N-PLL circuit, electronic apparatus, moving object, and determination method of reference frequency of fractional N-PLL circuit

Synthesizing method of signal having variable frequency and synthesizer of signal having variable frequency

Clock generation system with dynamic distribution bypass mode

Apparatus to reduce power of a charge pump

Oscillation circuit, oscillator, electronic apparatus, moving object, and frequency adjustment method of oscillator

Systems and methods for frequency domain calibration and characterization

Self-calibrating shared-component dual synthesizer

Phase locked loop including a varainductor

Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path

Method and apparatus for controlling supply voltage of clock and data recovery circuit

Time-to-digital converter and PLL circuit using the same

Cancellation of delta-sigma quantization noise within a fractional-N PLL with a nonlinear time-to-digital converter

Time-to-digital converter based on a voltage controlled oscillator

Time-to-voltage converter using a capacitor based digital to analog converter for quantization noise cancellation

Cancellation of spurious tones within a phase-locked loop with a time-to-digital converter

Hybrid analog and digital control of oscillator frequency

METHOD, CIRCUIT AND SYSTEM FOR DETECTING A LOCKED STATE OF A CLOCK SYNCHRONIZATION CIRCUIT

Auto frequency calibration for a phase locked loop and method of use

Clock generating device, electronic apparatus, moving object, clock generating method

System and method for an accuracy-enhanced DLL during a measure initialization mode

Method and apparatus for avoiding spurs in chip

Spread-spectrum phase locked loop circuit and method

Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data

Apparatus, system and method for controlling temperature and power supply voltage drift in a digital phase locked loop

Hybrid phase-locked loops

Method and apparatus for source-synchronous signaling

Delay-locked loop (DLL) circuit apparatus and method for locking thereof

Frequency control system with dual-input bias generator to separately receive management and operational controls

CIRCUITS, APPARATUSES, AND METHODS FOR DELAY MODELS

Signal distribution networks and related methods

Methods and systems for distributing clock and reset signals across an address macro

Methods and systems for determining whether a receiver is present on a PCI-express bus

Methods and systems for clocking a physical layer interface

Clock synchronization circuit and semiconductor memory device including clock synchronization circuit

Wave clocking

Delay Locked Loop

Area-efficient PLL with a low-noise low-power loop filter

Interface circuit for signal transmission

Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path

Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple

Clock recovery circuit and clock and data recovery circuit

Integrated circuits and methods for dynamic frequency scaling

Delay locked loop and method of generating clock

Semiconductor device

Clock regeneration circuit, light receiving circuit, photocoupler, and frequency synthesizer

Clock signal initialization circuit and its method

Low power data recovery

Delay line off-state control with power reduction

Circuits, apparatuses, and methods for delay models

Signal transmission circuit

Semiconductor chips and semiconductor systems for executing a test mode

Semiconductor device generating internal clock signal having higher frequency than that of input clock signal

Pre-heating for reduced subthreshold leakage

PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHS

Delay locked loop with a loop-embedded duty cycle corrector

Low power data recovery

Current output control device, current output control method, digitally controlled oscillator, digital PLL, frequency synthesizer, digital FLL, and semiconductor device

Clock and data recovery unit and power control method therefor and PON system

Auto frequency calibration for a phase locked loop and method of use

Method and apparatus for source-synchronous signaling

Systems and methods of low power clocking for sleep mode radios

Adaptive clock generating apparatus and method thereof

System and method for an accuracy-enhanced DLL during a measure initialization mode

Integrated circuit comprising a delay-locked loop

Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data

Phase locked loop circuitry having switched resistor loop filter circuitry, and methods of operating same

Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path

Integrated circuit for preventing chip swapping and/or device cloning in a host device

Methods of on-chip memory partitioning and secure access violation checking in a system-on-chip

Systems and methods for distributing an aging burden among processor cores

Adaptive clocking scheme to accommodate supply voltage transients

Apparatus and method to update a default time interval based on process corner, temperature and voltage

Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test mode

Proactive Power Management Using a Power Management Unit

Scalable and configurable system on a chip interrupt controller

Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device

Electronics device capable of efficient communication between components with asyncronous clocks

Integrated circuit with an adaptable contact pad reconfiguring architecture

Integrated circuit with pre-heating for reduced subthreshold leakage

Wave clocking

Time-based apparatus and method to mitigate semiconductor aging effects

Wide-range clock multiplier

Digital frequency locked loop

Delay line off-state control with power reduction

Radio apparatus

Radio apparatus

Signal distribution networks and related methods

Fractional digital PLL with analog phase error compensator

Spur reduction technique for sampling PLL's

Frequency synthesiser

Method using digital phase-locked loop circuit including a phase delay quantizer

Semiconductor device

Methods and apparatuses for delay-locked loops and phase-locked loops

Low power digital phase lock loop circuit

OSCILLATOR COMBINED CIRCUIT, SEMICONDUCTOR DEVICE, AND CURRENT REUSE METHOD

Low power clocking scheme for a pipelined ADC

Low power frequency divider and low power phase locked loop including the same

Clock generating circuit, semiconductor device including the same, and data processing system

Phase locked loop circuitry having switched resistor loop filter circuitry, and methods of operating same

Phase-locked loop circuit and communication apparatus

Digital phase-locked loop and digital phase-frequency detector thereof

Programmable Frequency Divider with Full Dividing Range

Clock and data recovery circuit

Digital phase-locked loop circuit including a phase delay quantizer and method of use

Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same

Clock divider and clock dividing method for a DLL circuit

System and method for an accuracy-enhanced DLL during a measure initialization mode

Delayed-locked loop with power-saving function

Digital PLL device

Delay line off-state control with power reduction

Delay locked loop circuit and method thereof

System and method of controlling power consumption in a digital phase locked loop (DPLL)

Look loop circuit and method having improved lock time

Automatic calibration lock loop circuit and method having improved lock time

Digital phase-locked loop with gated time-to-digital converter

Semiconductor integrated circuit and method of controlling the same

Method and apparatus for controlling a bias current of a VCO in a phase-locked loop

Wake-up circuit

Delay stage-interweaved analog DLL/PLL

Dividerless PLL architecture

DLL circuit

Electronic device and method for controlling current of a processor load by slewing clock frequency

OSCILLATOR

System and method for an accuracy-enhanced DLL during a measure initialization mode

Delayed locked loop circuit

FREQUENCY SYNTHESIZER AND METHOD FOR OPERATING A FREQUENCY SYNTHESIZER

FREQUENCY SYNTHESIZER AND METHOD FOR OPERATING A FREQUENCY SYNTHESIZER

Method and apparatus for timing and event processing in wireless systems