Fractional and integer PLL architectures

Clock recovery circuit

Predictive phase locked loop system

PHASE LOCK OSCILLATOR AND WIRELESS COMMUNICATIONS DEVICE INCLUDING PHASE LOCK OSCILLATOR

Method for generating a clock frequency

System and method for reducing lock time in a phase-locked loop

SPREAD SPECTRUM CLOCK GENERATOR CAPABLE OF FREQUENCY MODULATION WITH HIGH ACCURACY

Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL)

Spread spectrum clock generators

Clock generators and clock generation methods thereof

Frequency calibration apparatus of frequency synthesizer and frequency calibration method thereof

Signal generator with adjustable frequency

Method and system of jitter compensation

Green technologies: 7less microsystems

Fractional divider

Frequency reacquisition in a clock and data recovery device

4Less-TSOC of XLC, QBXOCK, QBTCXO, QBVCXO, SMLDVR and ANLVCO or 4Free-TSOC of XLC, QBXOCK, QBTCXO, QBVCXO, SMLDVR and ANLKVCO

Fractional-N phase locked loop

SEMICONDUCTOR DEVICE, MODULE INCLUDING THE SEMICONDUCTOR DEVICE, AND SYSTEM INCLUDING THE MODULE

Digital PLL and applications thereof

Method for noise reduction in a phase locked loop and a device having noise reduction capabilities

Methods and apparatus for frequency synthesis with feedback interpolation

Phase locked loop with phase shifted input

Phase locked loop circuit including digital voltage-controlled oscillator, ring oscillator and selector

Phase locked loop with phase rotation for spreading spectrum

HORIZONTAL SYNCHRONOUS CIRCUIT, DISPLAY DEVICE, AND CLOCK ADJUSTING METHOD

APPARATUS AND METHODS FOR CONTROLLING DELAY USING A DELAY UNIT AND A PHASE LOCKED LOOP

Semiconductor device

Phase locked loop with adaptive phase error compensation

Semiconductor memory device having low jitter source synchronous interface and clocking method thereof

Static phase adjust using LC tanks with offset center frequencies

Phase-locked loop capable of dynamically adjusting phase of output signal according to detection result of phase/frequency detector, and method thereof

Frequency agile phase locked loop

Hybrid phase-locked loop

Wide frequency range delay locked loop

METHOD AND APPARATUS FOR GENERATING CLOCK SIGNAL

Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation

Clock offset compensator

Phase-locked loop bandwidth calibration

Method and Integrated Circuit for Controlling an Oscillator Signal

Phase-locked loop

Adjustable phase controlled clock and data recovery circuit

Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit

Loop filtering for fast PLL locking

PLL frequency generator

Method and apparatus for measuring and compensating for static phase error in phase locked loops

Phase locked loop for controlling a recording device and method thereof

PLL frequency generator

Clock deskewing method, apparatus, and system

Phase interpolator with adaptive delay adjustment

Signal alignment based on data signal

PHASE LOCKED LOOP CIRCUIT

Phase-interpolator based PLL frequency synthesizer

Phase-locked loop and method for operating a phase-locked-loop

Clock signal generation using digital frequency synthesizer

Single chip GSM/EDGE transceiver architecture with closed loop power control

Direct conversion receiver having a subharmonic mixer

Variable gain frequency multiplier

Low jitter clock recovery circuit

Clock generation circuit and clock generation method

Semiconductor device, spread spectrum clock generator and method thereof

Clock recovery circuit

Process-insensitive self-biasing phase locked loop circuit and self-biasing method thereof

Data recovery using data eye tracking

Recovery of client clock without jitter

Clock generating circuit and clock generating method

Self-calibrating time code generator

Highly configurable PLL architecture for programmable logic

Phase-locked loop using multi-phase feedback signals

Method and system for wide-range synchronization to alternating current power signals

Method and apparatus for creating a multiple loop VCO

Phase frequency detector with programmable delay

Phase locked loop comprising a sigma-delta modulator

Method and apparatus for multi-mode clock data recovery

System and method for jitter control

Digital spread spectrum clock signal generation

Fast locking method and apparatus for frequency synthesis

Phase locked loop

PLL circuit

Phase-locked loop circuit

Delay locked loops and methods using ring oscillators

Temperature compensated crystal oscillator

Prescaler for a phase-locked loop circuit

Clock generating circuit

Jitter applying circuit and test apparatus

Frequency synthesizer architecture

Phase locked loop comprising a ΣΔ modulator

Phase locked loop with a modulator

Phase adjusting circuit for minimized irregularities at phase steps

Frequency synthesizer with digital phase selection

Signal generator with selectable mode control

Clock data recovery circuit

Highly configurable PLL architecture for programmable logic

Frequency division/multiplication with jitter minimization

Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer

Erroneous phase lock detection circuit

Clock generating circuit

Clock generator with one pole and method for generating a clock

Jitter-less phase detector in a clock recovery circuit

High spectral purity microwave oscillator using air-dielectric cavity

DPLL timing normalization

Apparatus and methods for a phase frequency detector with a wide operational range

Comb enhanced oscillator with AM-to-PM noise suppression

Molecular clock calibration

Tx-Rx synchronization for reflective optoelectronic systems in portable electronic devices

Sampling phase-locked loop

Methods and apparatus to implement pulse swallowing circuitry in a phase frequency detector

System, apparatus and method for mitigating digital interference within radio frequency circuitry

Fractional realignment techniques for PLLs

Calibration of an interpolative divider using a virtual phase-locked loop

Fractional realignment techniques for PLLs

Clock generating device and clock generating method

Metastable-free output synchronization for multiple-chip systems and the like

Scalable, electro-optically induced force system and method

Linearized time amplifier architecture for sub-picosecond resolution

Multi-ring cross-coupled voltage-controlled oscillator

Frequency agile modulator

Adaptive jitter and spur adjustment for clock circuits

Mechanism for adjusting characteristics of inter-stage circuit to mitigate or reduce DCO pulling effect

Circuit for and method of implementing a bursty clock and data recovery circuit using an eyescan detection circuit

Phase lock loop circuits and methods including multiplexed selection of feedback loop outputs of multiple phase interpolators

Method and device for high-speed sub-picosecond linear clock phase detection

Frequency estimation, correction and noise suppression for modems

Performance indicator for phase locked loops

Pre-synchronizer

Low-power phase interpolator with wide-band operation

Pre-distortion for a phase interpolator with nonlinearity

Clock synchronization

Non-disruptive eye scan for data recovery units based on oversampling