SYSTEMS AND METHODS FOR PROVIDING CLOCK SIGNALS

Tap Delay Line Phase Detector

CALIBRATION CIRCUIT TO SUPPRESS NON-LINEARITY

IMPLEMENTING A LOW POWER TOPOLOGY IN A CLOCKED LATCH

POWER CONVERSION SYSTEM HAVING SPREAD SPECTRUM AND PHASE SHIFTING MECHANISMS

DELAY LINE TEMPERATURE CALIBRATION

RESISTOR-ASSISTED SUPPLY SENSITIVITY IMPROVED RING OSCILLATOR FOR WIRELINE AND WIRELESS APPLICATIONS

PLL USING A DCO PERIOD LENGTH FEEDBACK CLOCK PULSE TO DETERMINE PHASE ERROR AND TDC GAIN

MIXED SIGNAL ELECTRONICS FOR LOCKING CONTROL OF HIGH-Q FEEDBACK LOOPS AND ASSOCIATED CIRCUITRY FOR DETECTING PHASE SHIFT OF A RESONATOR

PHASE-LOCKED LOOP CIRCUIT AND DISPLAY DRIVER INCLUDING SAME

SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION

DELAY ELEMENT GAIN CALIBRATION

SPREAD SPECTRUM CLOCK GENERATOR, MEMORY STORAGE DEVICE, AND SPREAD SPECTRUM CLOCK GENERATION METHOD

CASCADE COMMUNICATION DEVICE AND METHOD AND BATTERY MANAGEMENT SYSTEM

ANALOG-TO-DIGITAL CONVERTER (ADC) CLOCK PHASE CONTINUITY ACROSS USER EQUIPMENT MICROSLEEP MODE

HOOKAH DEVICE

FAST TRACKING PLL WITH ANALOG MIXER FOR PHASE DETECTION

CLOCK GENERATION DEVICE AND CLOCK GENERATION METHOD USING THE SAME

Systems and methods for PLL duty cycle calibration

SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, AND CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

Phase-locked loop device

Hookah device

MIST GENERATOR DEVICE

Hookah device

NICOTINE DELIVERY DEVICE

TD CONVERTER, PLL CIRCUIT, TD CONVERTING METHOD, AND CLOCK GENERATING METHOD

FOLDED RAMP GENERATOR

CLOCK SELECTION METHOD FOR MULTIPLYING DELAY LOCKED LOOP

Hookah device

Multiphase clock generators with digital calibration

Fractional divider with phase shifter and fractional phase locked loop including the same

Control circuit for an electronic converter, related integrated circuit, electronic converter and method

Adaptive cyclic delay line for fractional-N PLL

Clock recovery circuit, corresponding device and method

Controller and control techniques for linear accelerator and ion implanter having linear accelarator

Phase-locked loop circuit and operation method thereof

Time-to-digital converter (TDC) to operate with input clock signals with jitter

Counter design for a time-to-digital converter (TDC)

PHASE LOCK LOOP WITH AN ADAPTIVE LOOP FILTER

Fractional-n sub-sampling phase locked loop using phase rotator

Delay synchronization circuit, clock transmission circuit, and clock transmission and reception circuit

Circuits and methods to alter a phase speed of an output clock

PAM-4 receiver with jitter compensation clock and data recovery

Nicotine delivery device

Hookah device

Hookah device

Nicotine delivery device having a mist generator device and a driver device

Hookah device

Phase-locked loop circuit, configuration method therefor, and communication apparatus

Frequency dividing circuit, frequency dividing method and phase locked loop

Fractional sampling-rate converter to generate output samples at a higher rate from input samples

PLL circuit

Folded ramp generator

Frequency locking method and circuit for phase-locked loop

Control signal pulse width extraction-based phase-locked acceleration circuit and phase-locked loop system

High stability optoelectronic oscillator and method

Can transmitter

Integrated device having phase interpolator and input controller thereof

Nicotine delivery device with airflow arrangement

Nicotine delivery device with identification arrangement

Delay line structure and delay jitter correction method thereof

Phase locking circuit

Multi-modal data-driven clock recovery circuit

Rangefinder For A Telescope

Low integral non-linearity digital-to-time converter for fractional-N PLLS

Phase-locked loop circuit having linear voltage-domain time-to-digital converter with output subrange

Nicotine delivery device having a mist generator device and a driver device

Hookah device

Metastabile state detection device and method, and ADC circuit

Precision high frequency phase adders

Frequency locked loops and related circuits and methods

Digital subsampling PLL with DTC-based SAR phase estimation

Interface for semiconductor device and interfacing method thereof

System and method for low jitter phase-lock loop based frequency synthesizer

Calibration of sampling-based multiplying delay-locked loop (MDLL)

Circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops

Symmetrically-interconnected tunable time delay circuit

Secured communication by monitoring bus transactions using selectively delayed clock signal

Time-to-digital converter

Semiconductor device

Dynamic multiphase injection-locked phase rotator for electro-optical transceiver

Phase-locked loop circuit and digital-to-time convertor error cancelation method thereof

System for performing phase matching operation

Controller and control techniques for linear accelerator and ion implanter having linear accelerator

Circuit to correct phase interpolator rollover integral non-linearity errors

Folded ramp generator

Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops

Phase locked loop circuit

Signal generation circuit, memory storage device and signal generation method

Apparatus and method for improving lock time

DPLL restart without frequency overshoot

Phase-locked loop circuit and clock generator including the same

Locking technique for phase-locked loop

Display device and method of driving the same

SYSTEM AND METHOD FOR CORRECTING PHASE NOISE IN A COMMUNICATION SYSTEM

Precision High Frequency Phase Adders

Multi-modal data-driven clock recovery circuit

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop

Quadrature local oscillator signal generation systems and methods

Clock data recovery circuit

Clock and data recovery and associated signal processing method

Systems and methods for dynamic phase alignment of clocks

PHASE LOCKED LOOP

Tipless transistors, short-tip transistors, and methods and circuits therefor

Apparatus and method for improving lock time

Clock recovery system

Parallel fractional-N phase locked loop circuit

DPLL with adjustable delay in integer operation mode

Carrier recovery analog system for a receiver of a N-PSK signal

Calibration scheme for serialization in transmitter

Devices, systems, and methods for reducing jitter in control systems

Voltage controlled oscillator with reduced phase noise

System and method for hitless clock switching

Multi-chip synchronization with applications in multiple-input multiple-output (MIMO) radar systems

Phase measurement in a radar system

Test and characterization of an embedded PLL in an SOC during startup

Precision high frequency phase adders

PLL with Lock-in Frequency Controller

PLL with phase range extension

Phase accumulator with improved accuracy

Phase locked loop, phase locked loop arrangement, transmitter and receiver and method for providing an oscillator signal

Wobble reduction in an integer mode digital phase locked loop

Reducing chip latency at a clock boundary by reference clock phase adjustment

Wide range frequency synthesizer with quadrature generation and spur cancellation

Time-to-digital converter

Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops

Clock recovery circuits, systems and implementation for increased optical channel density

Locked loop circuit with configurable second error input

Phase calibration of clock signals

Full range realignment ring oscillator

Digitally assisted feedback loop for duty-cycle correction in an injection-locked PLL

Electric signal transmission device

Phase locked loop and control method therefor

FUNCTIONAL SAFETY CLOCKING FRAMEWORK FOR REAL TIME SYSTEMS

Synchronous clock generation using an interpolator

Multi-phase fractional divider

Multi-modal data-driven clock recovery circuit

Phase-locked loop

Frequency divider

Adjustments of output clocks

Fraction-N digital PLL capable of canceling quantization noise from sigma-delta modulator

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT DEVICE, ELECTRONIC DEVICE, AND VEHICLE

Precision high frequency phase adders

Low-power local oscillator generation

Phase-locked loop, phase-locking method, and communication unit

Tipless transistors, short-tip transistors, and methods and circuits therefor

Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator

Digital phase controlled PLLs

CONTROL CIRCUIT

Circuit to mitigate signal degradation in an isolation circuit

Lock detector for phase lock loop

Semiconductor device including DLL and semiconductor system

Method and circuit for controlling oscillator and apparatus employing the same

Digital fast lock for phase-locked loops

Low voltage differential signaling driver

Glitch free phase selection multiplexer enabling fractional feedback ratios in phase locked loops

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop

Synchronous clock generation using an interpolator

Duty-cycled phase shifter for angular rate sensor

Method of contactless communication between an object and a reader by active load modulation

Digital, reconfigurable frequency and delay generator with phase measurement

Phase calibration of clock signals

ANALOG FRACTIONAL-N PHASE-LOCKED LOOP

Deserialized dual-loop clock radio and data recovery circuit

DTC-based PLL and method for operating the DTC-based PLL

Wide range frequency synthesizer with quadrature generation and spur cancellation

Eddy current inspection instrument with noise shaping filter

Non-destructive inspection having phase amplitude modulation with time division multiplexing

Method for controlling digital fractional frequency-division phase-locked loop and phase-locked loop

Wide frequency range delay locked loop

Spread spectrum clock generator circuit

Clock data recovery circuit, integrated circuit including the same, and clock data recovery method

Forwarded clock receiver based on delay-locked loop

Clock generating apparatus and clock data recovering apparatus

Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator

Tipless transistors, short-tip transistors, and methods and circuits therefor

PHASE SYNCHRONIZATION WITH LOW FREQUENCY SAMPLING

Frequency synthesizer

Phase calibration of clock signals

Phase locked loop, wireless communication apparatus and wireless communication method

Dual path timing wander removal

Phase-rotating phase locked loop and method of controlling operation thereof

Hardware delay compensation in digital phase locked loop

Multi-wire open-drain link with data symbol transition based clocking

Phase locked loop having fractional VCO modulation

Methods and devices for error correction of a signal using delta sigma modulation

Fractional dividing module and related calibration method

Phase detector and associated phase detecting method

SEMICONDUCTOR DEVICE WITH TOUCH SENSOR CIRCUIT

Wideband digitally controlled injection-locked oscillator

Spread spectrum clock generator, electronic apparatus, and spread spectrum clock generation method

60 GHz frequency generator incorporating third harmonic boost and extraction

Switching current source radio frequency oscillator

Removing deterministic phase errors from fractional-N PLLs

Device for generating a clock signal by frequency multiplication

Frequency synthesizer for achieving fast re-lock between alternate frequencies in low bandwidth PLLs

System for digitally controlled edge interpolator linearization

Wide range frequency synthesizer with quadrature generation and spur cancellation

Reconfigurable fractional divider

Fractional PLL circuit

Clock generation circuit and method thereof

Locking multiple voltage-controlled oscillators with a single phase-locked loop

Multi-lane serial link signal receiving system

Electric and electronic apparatus, circuit, and communication system

Clock and data recovery device

Signal generation circuit and electronic apparatus

System and method for dynamic frequency estimation for a spread-spectrum digital phase-locked loop

Clock generating circuit, semiconductor device including the same, and data processing system

Synthesizing method of signal having variable frequency and synthesizer of signal having variable frequency

DIGITAL OUTPUT CLOCK GENERATION

Main clock high precision oscillator

On die jitter tolerance test

Electronic circuit and control method

Digital signal sampling method

Phase-rotating phase locked loop and method of controlling operation thereof

Method and apparatus for smoothing jitter generated by byte stuffing

Multi-wire open-drain link with data symbol transition based clocking

Low-power and all-digital phase interpolator-based clock and data recovery architecture

Phase locked loop frequency synthesizer with reduced jitter

Semiconductor device, radio communication terminal, and method for controlling semiconductor device

Multi-phase fractional divider

Circuit for measuring the resonant frequency of nanoresonators

Clock generating circuit

Interpolative divider linearity enhancement techniques

Clock and data recovery using LC voltage controlled oscillator and delay locked loop

Synchronous semiconductor device having delay locked loop for latency control

On die jitter tolerance test

Input jitter filter for a phase-locked loop (PLL)

Higher-order phase noise modulator to reduce spurs and quantization noise

Wide frequency range delay locked loop

Wide range frequency synthesizer with quadrature generation and spur cancellation

Low jitter clock recovery circuit

SEMICONDUCTOR DEVICE GENERATING PHASE-CONTROLLED CLOCK SIGNAL

Automatic detection and compensation of frequency offset in point-to-point communication

Clock and data recovery (CDR) architecture and phase detector thereof

Clock data recovery circuit

Time-to-digital system and associated frequency synthesizer

Frequency synthesizer and associated method

Frequency synthesizer and associated method

Multiplexing transmission system, receiver apparatus and module, transmitter apparatus for multiplexing transmission

Clock generating circuit, transceiver and related method

Method and apparatus for regenerating a pixel clock signal

Fractional and integer PLL architectures

Wide frequency range delay locked loop

Optimized synchronous strobe transmission mechanism

Apparatus and method for advanced synchronous strobe transmission

Spread spectrum clock generators and electronic devices including the same

Fractional frequency division or multiplication by using an oversampled phase rotator for reducing jitter

Frequency control clock tuning circuitry

Fast lock clock-data recovery for phase steps

Clock and data recovery using LC voltage controlled oscillator and delay locked loop

Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator

Low jitter clock recovery circuit

Frequency Offset Tracking and Jitter Reduction Method Using Dual Frequency-locked Loop and Phase-locked Loop

Phase-lock assistant circuitry

Digital phase-locked loop architecture

Phase-locked loop based frequency synthesizer and method of operating the same

Injection-locked oscillator

Phase detection method and phase detector

Phase locked loop and method for operating the same

Fractional-N phase locked loop, operation method thereof, and devices having the same

Host controller, semiconductor device and method for setting sampling phase

Phase interpolation-based clock and data recovery for differential quadrature phase shift keying

Phase-lock assistant circuitry

Hybrid data transmission circuit

Digital receivers

Highly flexible fractional frequency synthesizer

Wide frequency range delay locked loop

Electronic device for generating a fractional frequency

System and method for reducing lock time in a phase-locked loop

Repeate architecture with single clock multiplier unit

Clock synthesis systems, circuits and methods

Spread spectrum clock generators and electronic devices including the same

Digital phase locked loop

Phase locked loop and method for operating the same

Video horizontal synchronizer

Clock generating circuit, semiconductor device including the same, and data processing system

Apparatus and method for controlling the output phase of a VCO

Clock generating circuit, transceiver and related method

Signal generation apparatus and test apparatus

FREQUENCY SYNTHESIZER AND POLAR TRANSMITTER HAVING THE SAME

Phase interpolator with adaptive delay adjustment

Clock data recovery circuit and multiplied-frequency clock generation circuit

Fractional divider

Wireless apparatus

CLOCK DISTRIBUTION DEVICE AND CLOCK DISTRIBUTION METHOD

Phase shift phase locked loop

Clock generation circuit and system

Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control

Phase locked loop capable of fast locking

Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit

Method and apparatus for multi-mode clock data recovery

Digital phase lock loop with multi-phase master clock

Clock clean-up phase-locked loop (PLL)

Frequency adjustment for clock generator

Clock data recovery device

Systems and methods for distributing a clock signal

Frequency dividing device

Communication systems, clock generation circuits thereof, and method for generating clock signal

Method and apparatus for measuring and compensating for static phase error in phase locked loops