Method of switching PLL characteristics and PLL circuit

Timing vernier using a delay locked loop

Recovery circuits and methods for the same

Phase-locked loop with conditioned charge pump output

Phase locked loop with nonlinear phase-error response characteristic

Phase error cancellation

Spread spectrum clock generation circuit, jitter generation circuit and semiconductor device

Versatile feedback system for phase locked loop architecture

Low power and low timing jitter phase-lock loop and method

Capacitance multiplier with enhanced gain and low power consumption

Phase-locked loop with a pulse generator, and method for operating the phase-locked loop

Voltage controlled oscillator with automatic band selector

Method and apparatus for generating a sequence of clock signals

Circuit for compensating charge leakage in a low pass filter capacitor of PLL systems

Circuit for compensating LPF capacitor charge leakage in phase locked loop systems

Phase-locked loop circuits with reduced lock time

Methods and apparatuses for detecting clock loss in a phase-locked loop

Communication semiconductor integrated circuit and radio communication system

Phase-locked loop integrated circuits having fast phase locking characteristics

Frequency synthesizer, radio communication system using the synthesizer, and control method of the synthesizer

Synchronization circuit and synchronization method

DLL circuit with delay equal to one clock cycle

Circuit for generating spread spectrum clock

Phase locked loop with adaptive loop bandwidth

Tuning system

Loop filter for use in a phase-locked loop

Low-noise frequency divider

Compensating for leakage currents in loop filter capacitors in PLLs and the like

Phase locked loop and method for evaluating a jitter of a phase locked loop

Delay locked loop capable of preventing false lock and method thereof

Delay-locked loop

Programmable phase-locked loop circuitry for programmable logic device

Controlling a voltage controlled oscillator in a bang-bang phase locked loop

Digital-data receiver synchronization method and apparatus

Phase locked loop for generating an output signal

Semiconductor integrated circuit

Delay circuit with timing adjustment function

PLL circuit leakage compensation circuit for generating a leakage compensation signal

Charge pump circuit and PLL circuit using same

Charge pump circuit and PLL circuit using same

Charge leakage correction circuit for applications in PLLs

Programmable bandwidth during start-up for phase-lock loop

Programmable bandwidth and frequency slewing for phase-lock loop

Method for automatically calibrating the frequency range of a PLL and associated PLL capable of automatic calibration

Phase locked loop calibration

Integrated decision feedback equalizer and clock and data recovery

DC-DC converter connected to phase locked loop

On-chip loop filter for a PLL

Timing vernier using a delay locked loop

Linear half-rate phase detector and clock and data recovery circuit

Loop filter with active capacitor and method for generating a reference

Phase detector system with asynchronous output override

Dummy delay line based DLL and method for clocking in pipeline ADC

Phase frequency detector with programmable minimum pulse width

Leakage compensation circuit

Semiconductor device and PLL circuit

Programmable frequency detector for use with a phase-locked loop

System and method for signal amplification

PLL clock signal generation circuit

Delay-locked loop circuit and method thereof for generating a clock signal

Semidigital delay-locked loop using an analog-based finite state machine

Oscillation device and mobile communication apparatus

System and method for design entry and synthesis in programmable logic devices

Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same

Phase-locked-loop with reduced clock jitter

PLL circuit with simulation components to reduce phase offset

Programmable phase-locked loop circuitry for programmable logic device

RF converter with multiple mode frequency synthesizer compatible with a 48 Fo GPS baseband processor

Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit

Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof

Wireless communication semiconductor integrated circuit device and mobile communication system

PLL with swappable tuning loops

Current mirror compensation circuit and method

Current mirror compensation using channel length modulation

Method of controlling phase locked loop in mobile station, and mobile station

Low-noise loop filter for a phase-locked loop system

Method and apparatus for fast lock acquisition in self-biased phase locked loops

Voltage controlled oscillator, frequency synthesizer and communication apparatus

Device and method for detecting phase difference and PLL using the same

Phase locked loop circuit with self adjusted tuning hiep the pham

System and method for signal limiting

Dual-gain loop circuitry for programmable logic device

Circuit and method for faster frequency switching in a phase locked loop

Calibrating a loop-filter of a phase locked loop

Lock detectors having a narrow sensitivity range

Spectrum profile control for a PLL and the like

Clock generator with one pole and method for generating a clock

Circuit, apparatus and method for obtaining a lock state value

System and method for automatically correcting duty cycle distortion

Low jitter high phase resolution PLL-based timing recovery system

Controlled oscillation module

Clock generator with skew control

Rotational frequency detector system

PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications

Phase locked loop circuit

Spread-spectrum clock signal generator

Self-calibrating controllable oscillator

Phase-locked loop circuit with switched-capacitor conditioning of the control current

Subranging digital to time converter-based fractional phase locked loop architecture

Phase locked loop architecture with reduced bandwidth variation

Ring voltage controlled oscillator-based phase locked loop with dual charge pump architecture

Charge pump for fractional-n frequency synthesizer

Wideband rail-to-rail voltage controlled oscillator

LC-tank-based phase-locked loop (LCPLL)

Low-power, reduced-area VCO design with power supply noise rejection

Dual-structure acquisition circuit for frequency synthesis

Apparatus and methods for a phase frequency detector with a wide operational range

Clock data recovery circuit including charge pump having reduced glitch current

Phase locked loop pulse truncation

Reducing delay-lock loop delay fluctuation

Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection

High bandwidth CDR

Low-power fractional analog PLL without feedback divider

Methods and apparatus to implement pulse swallowing circuitry in a phase frequency detector

Phase-locked loop circuit, control method thereof and electronic device

Phase locked loop device and method of operating ihe same

Method of detecting jitter in clock of apparatus and apparatus utilizing same

Semiconductor integrated circuit, electronic device, and method of detecting frequency

Frequency detector for clock data recovery

Frequency domain-based clock recovery

Advanced multi-gain calibration for direct modulation synthesizer

Voltage-controlled oscillator circuit and phase-locked loop circuit

Method and circuits for reducing noise in phase-locked loops

Transmitter with reduced VCO pulling

Multi-path dual-switch digital-to-analog converter

Frequency synthesizer and method of operating the same

Sub-clock current pulse generator

PLL for continuous-time delta-sigma modulator based ADCs

High-speed linear charge pump circuits for clock data recovery

Frequency locked loop with multi-bit sampler

Duty cycle and skew correction for output signals generated in source synchronous systems

Duty cycle and skew correction for output signals generated in source synchronous systems

Microwave frequency synthesizers with rapid frequency switching

Charge pump circuit and PLL circuit

Realignment strength controller for solving loop conflict of realignment phase lock loop

Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops

Delay-locked loop having initialization circuit

Multi-mode frequency divider

Low-power wide-swing sense amplifier with dynamic output stage biasing

Referenceless clock and data recovery circuits

Clock recovery device and method

Fully integrated complete multi-band RF frontend system integrated circuit (IC) chip

On-chip jitter measurement for clock circuits

Gain calibration for direct modulation synthesizer using a look-up table searched by a reduced count from an overflow counter

Fast coarse tune and fine tune calibration for a synthesizer by multi-curve calibration within a target window

Digital linearization technique for charge pump based fractional phased-locked loop

Adaptively controlled duty cycle clock generation circuit

Voltage-mode SerDes with self-calibration

Differential charge pump with extended output control voltage range

Apparatus for linearizing a differential charge pump

Interpolating feedback divider

Techniques for signal skew compensation

Switched-capacitor circuits in a PLL

Self-calibrating fractional-N phase lock loop and method thereof

Method for reducing lock time in a closed loop clock signal generator

All-digital delay-locked loop circuit based on time-to-digital converter and control method thereof

Fast-response hybrid lock detector

Techniques for reducing skew between clock signals

Performance indicator for phase locked loops

Phase-locked loop circuit and calibrating method thereof

System and method for controlling a voltage controlled oscillator

Method and apparatus for multi-rate clock generation

Phase-locked loop having sampling phase detector

Integrated circuit device with on-board calibration of signal generator circuits, and related methods

Frequency synthesizer and method for frequency synthesis

Synchronization of outputs from multiple digital-to-analog converters

Glitch free bandwidth-switching scheme for an analog phase-locked loop (PLL)

Delay-locked loop circuit with fractional phase frequency detector

Feedback control system with rising and falling edge detection and correction

Programmable frequency divider providing output with reduced duty-cycle variations over a range of divide ratios

Charge pump strength calibration and screening in circuit design

Phase-locked loop with frequency bounding circuit

Delay-locked loop with false-lock detection and recovery circuit

Systems and methods involving fast-acquisition lock features associated with phase locked loop circuitry

Data receiver

Apparatus and method for dynamically providing charge

Fully differential charge pump with switched-capacitor common-mode feedback

Systems and methods of phase frequency detection involving features such as improved clock edge handling circuitry/aspects

DC-to-DC voltage converter using switching frequency detection

Time-to-digital converter

Time-to-digital conversion

Clock generator for use in a time-interleaved ADC and methods for use therewith

High resolution sampling-based time to digital converter