DUAL-PATH PHASE-LOCKED LOOP

AN APPARATUS

PHASE-LOCKED LOOP

Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation

TRIPLE-PATH CLOCK AND DATA RECOVERY CIRCUIT, OSCILLATOR CIRCUIT AND METHOD FOR CLOCK AND DATA RECOVERY

DUAL MODE PHASE-LOCKED LOOP CIRCUIT, OSCILLATOR CIRCUIT, AND CONTROL METHOD OF OSCILLATOR CIRCUIT

SYSTEMS AND METHODS FOR IMPROVED CHARGE PUMP PHASE-LOCKED LOOP PHASE STABILITY

CHARGE PUMP, PHASE-LOCKED LOOP, RADAR SENSOR, AND ELECTRONIC DEVICE

BUFFER CIRCUIT, AND SEMICONDUCTOR APPARATUS CAPABLE OF ADJUSTING A CLOCK RECEIVER AND/OR CHANGING A CLOCK PATH ACCORDING TO FREQUENCY INFORMATION

Systems and methods for improved charge pump phase-locked loop phase stability

Dual mode phase-locked loop circuit, oscillator circuit, and control method of oscillator circuit

TRIPLE-PATH CLOCK AND DATA RECOVERY CIRCUIT, OSCILLATOR CIRCUIT AND METHOD FOR CLOCK AND DATA RECOVERY

Adjustable phase locked loop

Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation

Successive-approximation register analog-to-digital converter circuit and operating method thereof

Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods

Low noise phase lock loop (PLL) circuit

Triple-path clock and data recovery circuit, oscillator circuit and method for clock and data recovery

Systems and methods for phase locked loop realignment with skew cancellation

Adjustable phase locked loop

DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT

Phase Locked Loop with Low Reference Spur

Systems and methods for phase locked loop realignment with skew cancellation

Monitor circuitry for power management and transistor aging tracking

Monitor circuitry for power management and transistor aging tracking

Successive-approximation register analog-to-digital converter circuit and operating method thereof

Dual mode phase-locked loop circuit, oscillator circuit, and control method of oscillator circuit

Triple-path clock and data recovery circuit, oscillator circuit and method for clock and data recovery

Charge pump circuit, PLL circuit, and oscillator

Lock detection circuit and phase-locked loop circuit

Charge pump, PLL circuit, and oscillator

DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT

DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT

Method and apparatus for calibration of voltage controlled oscillator

Phase locked loop

Clock signal generating circuit and method for generating clock signal

Phase locked loop circuits, clock signal generators comprising digital-to-time convert circuits, operating methods thereof and wireless communication devices

Circuit device, oscillator, electronic apparatus and moving object

Low power and low jitter phase locked loop with digital leakage compensation

Clock generator circuit and clock generating method

Apparatus and methods for timing offset compensation in frequency synthesizers

Bandwidth adjustment in a phase-locked loop of a local oscillator

Phase locked loop circuits, clock signal generators comprising digital-to-time convert circuits, operating methods thereof and wireless communication devices

Variable delay

Clock generator

Jitter reduction techniques when using digital PLLs with ADCs and DACs

Phase locked loop (PLL)

Low-jitter phase-locked loop circuit

Phase locked loops having decoupled integral and proportional paths

Method and apparatus for calibration of voltage controlled oscillator

Phase-locked loop circuit

Phase locked loop and associated method for loop gain calibration

Fractional-N frequency synthesizer incorporating cyclic digital-to-time and time-to-digital circuit pair

Fractional-N all digital phase locked loop incorporating look ahead time to digital converter

Split transformer based digitally controlled oscillator and DC-coupled buffer circuit therefor

Split transformer based LC-tank digitally controlled oscillator

Clock and data recovery apparatus

Phase-locked loop circuit with improved performance

Capacitance multiplier and loop filter noise reduction in a PLL

Charge pump calibration for dual-path phase-locked loop

Injection-locked phase locked loop circuits using delay locked loops

Frequency control system with dual-input bias generator to separately receive management and operational controls

PLL circuit

Clock and data recovery tolerating long consecutive identical digits

Area-efficient PLL with a low-noise low-power loop filter

Phase locked loop and method for operating the same

Frequency sweep signal generator, frequency component analysis apparatus, radio apparatus, and frequency sweep signal generating method

Correcting for offset-errors in a PLL/DLL

Sub-gate delay adjustment using digital locked-loop

Charge pump circuit

Phase-locked loop circuit

High-linearity phase frequency detector

Capacitive multiplication in a phase locked loop

Circuits and methods for a combined phase detector

System and method of stabilizing charge pump node voltage levels

Charge pump circuit with low clock feed-through

Gyroscope with phase and duty-cycle locked loop

Reducing phase locked loop phase lock time

SEMICONDUCTOR INTEGRATED CIRCUIT

Fully differential adaptive bandwidth PLL with differential supply regulation

High speed DLL offset cancellation

Phase locked loop with charge pump

Charge pump and active filter for a feedback circuit

Single-event upset hardened ring oscillator

Differential controlled phase locked loop circuit

Phase locked loop

Oscillator circuit and electric-current correction method

Synchronization of multiple high frequency switching power converters in an integrated circuit

Calibration for phase-locked loop

Frequency Synthesizer

Phase-locked loop with switched phase detectors

High speed charge pump

Loop filter and phase locked loop including the same

Semiconductor integrated circuit

Phase lock loop and control method thereof

Phase-locked loop

Phase-locked loop

Phase locked loop circuits and gain calibration methods thereof

Phase lock loop circuits

PLL circuit with VCO gain control

PLL circuit

Radiation-hardened charge pump topology

Phase-locked loop circuit and related phase locking method

Phase locked loop capable of fast locking

Calibration system and method for phase-locked loops

Phase locked loop

Wide dynamic range charge pump

Voltage-controlled oscillator, phase-locked loop (PLL) circuit, and clock generator

Phase-locked loop circuit, recording-and-reproducing apparatus, and electronic apparatus

Phase-locked loop circuit, recording-and-reproducing apparatus, and electronic apparatus

Voltage-controlled oscillator, phase-locked loop circuit and clock data recovery circuit

PLL CIRCUIT

System and method for effectively implementing a loop filter device

Frequency synthesizer

Method and apparatus for reducing spurs in a fractional-N synthesizer

Self-biased phase locked loop

Phase-locked loop circuit employing capacitance multiplication

Architecture for maintaining constant voltage-controlled oscillator gain

Self-biased phase locked loop and phase locking method

Variable loop bandwidth phase locked loop

Mutual charge cancelling sample-reset loop filter for phase locked loops

Phase locked loop

Phase lock loop apparatus

Phase-locked circuit employing capacitance multiplication

Semiconductor integrated circuit

Phase locked loop and method for controlling the same

PLL CIRCUIT

Bias voltage generation circuit and clock synchronizing circuit

Loop filter, phase-locked loop, and method of operating the loop filter

Dual path phase locked loop (PLL) with digitally programmable damping

CONTINUOUS GAIN COMPENSATION AND FAST BAND SELECTION IN A MULTI-STANDARD, MULTI-FREQUENCY SYNTHESIZER

Phase locked loop circuit having regulator

Frequency synthesizer with a harmonic locked phase/frequency detector

Methods and apparatus for frequency synthesis with feedback interpolation

Phase locked loop and delay locked loop with chopper stabilized phase offset

Decreasing frequency synthesizer lock time for a phase locked loop

System and method for reducing transient responses in a phase lock loop with variable oscillator gain

JITTER SMOOTHING FILTER

PLL circuit

PLL circuit and method of controlling the same

PLL circuit

DELAY LOCKED LOOP HAVING CHARGE PUMP GAIN INDEPENDENT OF OPERATING FREQUENCY

Delay locked loop having charge pump gain independent of operating frequency

Analog phase controller

Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation

PLL circuit

Continuous gain compensation and fast band selection in a multi-standard, multi-frequency synthesizer

Loop filter with noise cancellation

Semiconductor integrated circuit having built-in PLL circuit

Method for mitigating single event effects in a phase locked loop

Variable delay clock circuit and method thereof

Delay lock clock synthesizer and method thereof

Frequency independent control

Delay locked loop having charge pump gain independent of operating frequency

PLL CIRCUIT

Fast lock scheme for phase locked loops and delay locked loops

Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL

Semiconductor integrated circuit having built-in PLL circuit

Sigma-delta fractional-N PLL with reduced frequency error

Phase-locked loop systems and methods

Phase interpolation for phase-locked loops

Self-biased phased-locked loop

Phase-locked loop with tunable-transfer function

Clock and data recovery with extended integration cycles

Spread ratio fixing circuit and method for generating spread spectrum clock

Method and apparatus for capacitance multiplication within a phase locked loop

Type II phase locked loop using dual path and dual varactors to reduce loop filter components

Variable loop bandwidth phase locked loop

Phase locked loop filter

Charge pump structure for reducing capacitance in loop filter of a phase locked loop

Active filter in PLL circuit

Suppressing noise in a frequency synthesizer

CLOCK RECOVERY CIRCUIT AND CLOCK RECOVERY METHOD

Process-insensitive self-biasing phase locked loop circuit and self-biasing method thereof

Clock and data recovery circuit and method thereof

Self-biased phased-locked loop

Method and apparatus for loop filter size reduction

Phase-locked loop circuit

Startup/yank circuit for self-biased phase-locked loops

Phase locked loop

Phase-locked loop with a digital calibration loop and an analog calibration loop

Loop filter integration in phase-locked loops

Phase-locked loop circuits with current mode loop filters

PLL circuit and program for same

Phase locked loop

Phase-locked loops

Integrated CMOS clock generator with a self-biased phase locked loop circuit

Method and apparatus to achieve a process, temperature and divider modulus independent PLL loop bandwidth and damping factor using open-loop calibration techniques

Phase lock loop device

Phase locked loop circuit

Phase and delay locked loops and semiconductor memory device having the same

Circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PPLs)

Phase comparison circuit and CDR circuit

Variation tolerant charge leakage correction circuit for phase locked loops

Semiconductor integrated circuit having built-in PLL circuit

Spread spectrum clock generator

Phase locked loop integrated circuits having fast locking characteristics and methods of operating same

Phase-locked loop with conditioned charge pump output

Voltage controlled LC tank oscillator

Phase locked loop circuit

Loop filter integration in phase-locked loops

Phase-locked loops

Control signal generation for a low jitter switched-capacitor frequency synthesizer

Switched capacitor ripple-smoothing filter

Adaptive frequency detector of phase locked loop

Charge pump circuit reducing noise and charge error and PLL circuit using the same

Error-compensated charge pump circuit, and method for producing an error-compensated output current from a charge pump circuit

Phase locked loop with adaptive loop bandwidth

Frequency synthesizer for a wireless communication system

Phase locked loop and method for evaluating a jitter of a phase locked loop

Yank detection circuit for self-biased phase locked loops

Calibratable phase-locked loop

Compensation technique to mitigate aging effects in integrated circuit components

Semiconductor integrated circuit having built-in PLL circuit

PLL circuit having reduced capacitor size

Frequency and phase correction in a phase-locked loop (PLL)

Low-jitter charge-pump phase-locked loop

Generating an oscillating signal according to a control current

Variation of effective filter capacitance in phase lock loop circuit loop filters

Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit

Phase-locked loop bandwidth calibration circuit and method thereof

PLL with multiple tuning loops

Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL

Metal programmable phase-locked loop

Adaptive loop bandwidth circuit for a PLL

Compensating method for a PLL circuit that functions according to the two-point principle, and PLL circuit provided with a compensating device

PLL employing a sample-based capacitance multiplier

PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications

Jitter and reference spur management with adaptive gain by voltage controlled oscillator calibration

Charge pump with voltage tracking

Glitch free clock switching circuit

Glitch free clock switching circuit

Voltage regulator based loop filter for loop circuit and loop filtering method

Dual path phase-locked loop circuit

Reducing transient response in a phase-locked loop circuit

Phase locked loop calibration for synchronizing non-constant frequency switching regulators