222201 ⎘
Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop; Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
Sub-classes:CASCADED MULTI-LOOP PHASE LOCKED LOOP (PLL) CLOCK SYNCHRONIZER TOLERANT TO FAILURE OF INTERMEDIATE LOOPS
#2Digtal Phase-locked Loop with Digital Loop Filter Comprising Noise Cancellation Path, and Method of Operating Same
#3CLOCK DUTY CYCLE CALIBRATION CIRCUIT, METHOD, AND CLOCK MULTIPLIER CIRCUIT
#4METHODS AND APPARATUS OF CHARGE-SHARING LOCKING WITH DIGITAL CONTROLLED OSCILLATORS
#5SEMICONDUCTOR DEVICE
#6LINEAR PREDICTION TO SUPPRESS SPURS IN A DIGITAL PHASE-LOCKED LOOP
#7Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods
#8PHASE-LOCKED LOOPS (PLL) INCLUDING DIGITALLY CONTROLLED OSCILLATOR (DCO) GAIN CALIBRATION CIRCUITS AND RELATED METHODS
#9Phase estimation for high frequency signals
#10Delta-sigma modulator with modified quantization error shaping
#11Apparatus and method for optimum loop gain calibration for clock data recovery and phase locked loop
#12CLOCK SYNTHESIZER
#13METHODS AND APPARATUS OF CHARGE-SHARING LOCKING WITH DIGITAL CONTROLLED OSCILLATORS
#14DOUBLY-BALANCED AUTO-ZERO LFPS AND SQUELCH DETECTION
#15Methods and systems for controlling frequency and phase variations for PLL reference clocks
#16Methods and systems for controlling frequency variation for a PLL reference clock
#17Automatic Hybrid Oscillator Gain Adjustor Circuit
#18METHOD FOR CHANGING A BITWIDTH OF AN FPGA CONFIGURATION
#19Low power quadrature phase detector
#20Linear prediction to suppress spurs in a digital phase-locked loop
#21Methods and apparatus of charge-sharing locking with digital controlled oscillators
#22All-digital phase-locked loop and calibration method thereof
#23Automatic Hybrid Oscillator Gain Adjustor Circuit
#24Apparatus and methods for digital fractional phase locked loop with a current mode low pass filter
#25Clock and data recovery circuit, memory storage device and signal generating method
#26Connection interface circuit, memory storage device and phase-locked loop circuit calibration method
#27Apparatus and method for improving lock time
#28Phase-locked loop (PLL) circuit and clock generator including sub-sampling circuit
#29Feedback control for accurate signal generation
#30Apparatus and method for improving lock time
#31Phase locked loop frequency shift keying demodulator using an auxiliary charge pump and a differential slicer
#32Frequency synthesis with accelerated locking
#33Fast settling ramp generation using phase-locked loop
#34PLL circuit
#35Adaptive bandwidth systems and methods
#36Fast settling sawtooth ramp generation in a phase-locked loop
#37Coherent phase-synchronizing circuit
#38Switched-capacitor loop filter
#39Synchronization system for power generation unit and method thereof
#40Oscillator
#41Self-adapting phase-locked loop filter for use in a read channel of a heat assisted magnetic recording drive
#42PLL circuit and operation method
#43FREQUENCY SYNTHESIZER CIRCUIT
#44Phase-rotating phase locked loop and method of controlling operation thereof
#45Autoconfigurable Phase-Locked Loop Which Automatically Maintains a Constant Damping Factor and Adjusts the Loop Bandwidth to a Constant Ratio of the Reference Frequency
#46Biological information measurement method and apparatus with variable loop filter
#47Phase-rotating phase locked loop and method of controlling operation thereof
#48Device and method for preventing lost synchronization
#49Semiconductor device and radio communication terminal mounting the same
#50Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency
#51Clock generation system
#52Frequency synthesiser
#53Phase-locked loop
#54Frequency synthesizer
#55System and method for reducing lock time in a phase-locked loop
#56DELAY CIRCUIT
#57Local oscillator with injection pulling suppression and spurious products filtering
#58System and method for ESD protection
#59Frequency synthesizer
#60Phase-locked loop circuits and methods implementing multiplexer circuit for fine tuning control of digitally controlled oscillators
#61Phase synchronization circuit and receiver having the same
#62System and method for reducing lock time in a phase-locked loop
#63Transistor voltage-controlled oscillator and frequency synthesizer having the same
#64Synthesizer characterization in real time
#65Analogue self-calibration method and apparatus for low noise, fast and wide-locking range phase locked loop
#66Method and apparatus for providing a dual-loop phase lock loop
#67CONTINUOUS GAIN COMPENSATION AND FAST BAND SELECTION IN A MULTI-STANDARD, MULTI-FREQUENCY SYNTHESIZER
#68Phase Locked Loop with Stabilized Dynamic Response
#69Device and method for preventing lost synchronization
#70Noise canceling technique for frequency synthesizer
#71Device for generating counter signals representative of clock signals and device for reconstructing clock signals, for a packet-switched network
#72TUNABLE CAPACITANCE MULTIPLIER CIRCUIT
#73High resolution digitally controlled oscillator
#74Continuous gain compensation and fast band selection in a multi-standard, multi-frequency synthesizer
#75Communication semiconductor integrated circuit device and wireless communication system
#76Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL
#77Adaptive delay-locked loops and methods of generating clock signals using the same
#78Digital PLL circuit and optical disk apparatus having digital PLL circuit
#79Sigma-delta fractional-N PLL with reduced frequency error
#80Current-mode gain-splitting dual-path VCO
#81Low jitter and/or fast lock-in clock recovery circuit
#82Wireless communication system
#83Local oscillator with injection pulling suppression and spurious products filtering
#84PLL circuit with self-selecting variable divide ratio
#85Analogue self-calibration method and apparatus for low noise, fast and wide-locking range phase locked loop
#86Phase locked loop circuit having reduced lock time
#87Communication semiconductor integrated circuit device and wireless communication system
#88Tunable high-speed frequency divider
#89Adaptive phase recovery
#90Digital expander for generating multiple analog control signals particularly useful for controlling an oscillator
#91Phase-locked loop having a bandwidth related to its input frequency
#92Circuit, control system, IC, transmitting and receiving apparatus, control method and program
#93Semiconductor integrated circuit for communication
#94Method to configure phase-locked loop dividing ratio
#95Method for synchronizing exporter and exciter clocks
#96Oscillator
#97Variable lock-in circuit for phase-locked loops
#98Z-state circuit for delay-locked loops
#99Damping coefficient variation mechanism in a phase locked loop
#100High speed clock and data recovery system
#101Integrated circuit television receiver arrangement
#102Local oscillator circuit
#103Programmable bandwidth during start-up for phase-lock loop
#104Programmable bandwidth and frequency slewing for phase-lock loop
#105Digital expander apparatus and method for generating multiple analog control signals particularly useful for controlling an oscillator
#106Adaptively extending tunable range of frequency in a closed loop
#107Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL
#108Adaptive loop bandwidth circuit for a PLL
#109Frequency stabilized and phase noise suppressed microwave source using an IQ mixer to detect amplitude modulation and phase perturbation of the reflected signal
#110Low-pass filtering system having phase-locked loop
#111Bandwidth adjustability in an FMCW PLL system
#112Apparatus and methods for digital fractional phase locked loop with a current mode low pass filter